Re-run update.sh

rp-rs · Dec 7, 2024 · 98a016a · 98a016a
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diff --git a/src/inner/accessctrl/adc0.rs b/src/inner/accessctrl/adc0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<ADC0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, ADC0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<ADC0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<ADC0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, ADC0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<ADC0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<ADC0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<ADC0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<ADC0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<ADC0_SPEC> {
         DBG_W::new(self, 7)
     }

diff --git a/src/inner/accessctrl/busctrl.rs b/src/inner/accessctrl/busctrl.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<BUSCTRL_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<BUSCTRL_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<BUSCTRL_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, BUSCTRL can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<BUSCTRL_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<BUSCTRL_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<BUSCTRL_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<BUSCTRL_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<BUSCTRL_SPEC> {
         DBG_W::new(self, 7)
     }

diff --git a/src/inner/accessctrl/cfgreset.rs b/src/inner/accessctrl/cfgreset.rs
@@ -7,7 +7,6 @@ pub type CFGRESET_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cfgreset(&mut self) -> CFGRESET_W<CFGRESET_SPEC> {
         CFGRESET_W::new(self, 0)
     }

diff --git a/src/inner/accessctrl/clocks.rs b/src/inner/accessctrl/clocks.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<CLOCKS_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, CLOCKS can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<CLOCKS_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<CLOCKS_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, CLOCKS can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<CLOCKS_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<CLOCKS_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<CLOCKS_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<CLOCKS_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<CLOCKS_SPEC> {
         DBG_W::new(self, 7)
     }

diff --git a/src/inner/accessctrl/coresight_periph.rs b/src/inner/accessctrl/coresight_periph.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<CORESIGHT_PERIPH_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<CORESIGHT_PERIPH_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<CORESIGHT_PERIPH_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<CORESIGHT_PERIPH_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<CORESIGHT_PERIPH_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<CORESIGHT_PERIPH_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<CORESIGHT_PERIPH_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<CORESIGHT_PERIPH_SPEC> {
         DBG_W::new(self, 7)
     }

diff --git a/src/inner/accessctrl/coresight_trace.rs b/src/inner/accessctrl/coresight_trace.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<CORESIGHT_TRACE_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<CORESIGHT_TRACE_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<CORESIGHT_TRACE_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<CORESIGHT_TRACE_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<CORESIGHT_TRACE_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<CORESIGHT_TRACE_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<CORESIGHT_TRACE_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<CORESIGHT_TRACE_SPEC> {
         DBG_W::new(self, 7)
     }

diff --git a/src/inner/accessctrl/dma.rs b/src/inner/accessctrl/dma.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<DMA_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, DMA can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<DMA_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<DMA_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, DMA can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<DMA_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<DMA_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<DMA_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<DMA_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<DMA_SPEC> {
         DBG_W::new(self, 7)
     }

diff --git a/src/inner/accessctrl/force_core_ns.rs b/src/inner/accessctrl/force_core_ns.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<FORCE_CORE_NS_SPEC> {
         CORE1_W::new(self, 1)
     }

diff --git a/src/inner/accessctrl/gpio_nsmask0.rs b/src/inner/accessctrl/gpio_nsmask0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_nsmask0(&mut self) -> GPIO_NSMASK0_W<GPIO_NSMASK0_SPEC> {
         GPIO_NSMASK0_W::new(self, 0)
     }

diff --git a/src/inner/accessctrl/gpio_nsmask1.rs b/src/inner/accessctrl/gpio_nsmask1.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_NSMASK1_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_NSMASK1_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_NSMASK1_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_NSMASK1_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_NSMASK1_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_NSMASK1_SPEC> {
         QSPI_SD_W::new(self, 28)
     }