Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

RISC-V support over CLINT #815

Merged
merged 39 commits into from
Mar 20, 2024
Merged
Show file tree
Hide file tree
Changes from 38 commits
Commits
Show all changes
39 commits
Select commit Hold shift + click to select a range
59cde3e
Rebase to master
romancardenas Oct 6, 2023
a27bdbd
using interrupt_mod
romancardenas Oct 6, 2023
e50bff6
bug fixes
romancardenas Oct 6, 2023
aa5c92b
fix other backends
romancardenas Oct 6, 2023
0b74452
Add changelog
romancardenas Oct 6, 2023
bb78e98
forgot about rtic-macros
romancardenas Oct 6, 2023
79ec8a9
backend-specific configuration
romancardenas Oct 6, 2023
938cb9f
core peripherals optional over macro argument
romancardenas Oct 9, 2023
dcac6a1
pre_init_preprocessing binding
romancardenas Oct 9, 2023
535570f
CI for RISC-V (WIP)
romancardenas Nov 16, 2023
ee25c0a
separation of concerns
romancardenas Nov 24, 2023
2319064
add targets for RISC-V examples
romancardenas Nov 24, 2023
ef91d0c
remove qemu feature
romancardenas Dec 28, 2023
dafd8f2
prepare examples folder
romancardenas Dec 28, 2023
123ab23
move examples all together
romancardenas Dec 29, 2023
02a34ae
move ci out of examples
romancardenas Dec 29, 2023
4e4d0b7
minor changes
romancardenas Dec 29, 2023
e9a0ffc
add cortex-m
romancardenas Dec 29, 2023
e34bb5c
new xtask: proof of concept
romancardenas Dec 31, 2023
1493d1a
fix build.yml
romancardenas Dec 31, 2023
c68824d
feature typo
romancardenas Dec 31, 2023
584461f
clean rtic examples
romancardenas Dec 31, 2023
d8d731c
reproduce weird issue
romancardenas Jan 10, 2024
53dc2f1
remove unsafe code in user app
romancardenas Jan 11, 2024
e3cfa2c
update dependencies
romancardenas Jan 25, 2024
e88d40f
allow builds on riscv32imc
romancardenas Jan 25, 2024
3f9507c
let's fix QEMU
romancardenas Jan 25, 2024
68fa940
Update .github/workflows/build.yml
romancardenas Feb 15, 2024
045563e
New build.rs
romancardenas Feb 16, 2024
84818d7
removing test features
romancardenas Feb 16, 2024
6eacc13
adapt ui test to new version of clippy
romancardenas Feb 16, 2024
b2428b8
add more examples to RISC-V backend
romancardenas Feb 19, 2024
5aff1e4
proper configuration of heapless for riscv32imc
romancardenas Feb 19, 2024
bb17312
opt-out examples for riscv32imc
romancardenas Feb 19, 2024
da078d8
point to new version of riscv-slic
romancardenas Feb 27, 2024
dbcfe03
adapt new macro bindings
romancardenas Feb 27, 2024
1debe31
adapt examples and CI to stable
romancardenas Feb 27, 2024
27da4a2
fix cortex-m CI
romancardenas Feb 27, 2024
97b434c
Review
romancardenas Mar 7, 2024
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
157 changes: 134 additions & 23 deletions .github/workflows/build.yml
Original file line number Diff line number Diff line change
Expand Up @@ -31,9 +31,9 @@ jobs:
- name: cargo xtask fmt
run: cargo xtask --verbose fmt -c

# Compilation check
check:
name: check
# Compilation check (lm3s6965)
checklm3s6965:
name: check (lm3s6965)
runs-on: ubuntu-22.04
strategy:
matrix:
Expand Down Expand Up @@ -62,11 +62,14 @@ jobs:
- name: Cache Dependencies
uses: Swatinem/rust-cache@v2

- run: cargo xtask --deny-warnings --backend ${{ matrix.backend }} check
- run: cargo xtask --deny-warnings --platform lm3s6965 --backend ${{ matrix.backend }} check

# Clippy
clippy:
name: clippy
# Compilation check (hifive1) TODO
# checkhifive1:

# Clippy (lm3s6965)
clippylm3s6965:
name: clippy (lm3s6965)
runs-on: ubuntu-22.04
strategy:
matrix:
Expand Down Expand Up @@ -98,11 +101,14 @@ jobs:
- name: Cache Dependencies
uses: Swatinem/rust-cache@v2

- run: cargo xtask --deny-warnings --backend ${{ matrix.backend }} clippy
- run: cargo xtask --deny-warnings --platform lm3s6965 --backend ${{ matrix.backend }} clippy

# Clippy (hifive1) TODO
# clippyhifive1:

# Verify all examples, checks
checkexamples:
name: check examples
# Platform lm3s6965: verify all examples, checks
checkexampleslm3s6965:
name: check examples (lm3s6965)
runs-on: ubuntu-22.04
strategy:
matrix:
Expand Down Expand Up @@ -133,13 +139,48 @@ jobs:

- name: Check the examples
if: ${{ matrix.backend == 'thumbv8-base' }}
run: cargo xtask --backend ${{ matrix.backend }} --exampleexclude pool example-check
run: cargo xtask --platform lm3s6965 --backend ${{ matrix.backend }} --exampleexclude pool example-check

- name: Check the examples
if: ${{ matrix.backend != 'thumbv8-base' }}
run: cargo xtask --backend ${{ matrix.backend }} example-check
run: cargo xtask --platform lm3s6965 --backend ${{ matrix.backend }} example-check

# Platform hifive1: verify all examples, checks
checkexampleshifive1:
name: check examples (hifive1)
runs-on: ubuntu-22.04
strategy:
matrix:
backend:
- riscv32-imc-clint
- riscv32-imac-clint
toolchain:
- stable
steps:
- name: Checkout
uses: actions/checkout@v4

- name: Install Rust ${{ matrix.toolchain }}
run: |
rustup override set ${{ matrix.toolchain }}

- name: Configure Rust target
run: |
rustup target add riscv32imac-unknown-none-elf
rustup target add riscv32imc-unknown-none-elf

- name: Cache Dependencies
uses: Swatinem/rust-cache@v2

- name: Check the examples
if: ${{ matrix.backend == 'riscv32-imc-clint' }}
run: cargo xtask --platform hifive1 --backend ${{ matrix.backend }} --exampleexclude static example-check

- name: Check the examples
if: ${{ matrix.backend != 'riscv32-imc-clint' }}
run: cargo xtask --platform hifive1 --backend ${{ matrix.backend }} example-check

# Check that the usage examples build
# Check that the usage examples build TODO this would not be needed now
usageexamples:
name: Build usage examples
runs-on: ubuntu-22.04
Expand All @@ -161,6 +202,8 @@ jobs:
rustup target add thumbv7em-none-eabihf
rustup target add thumbv7m-none-eabi
rustup target add thumbv6m-none-eabi
rustup target add riscv32imc-unknown-none-elf
rustup target add riscv32imac-unknown-none-elf
rustup component add rust-src

- name: Cache Dependencies
Expand Down Expand Up @@ -192,7 +235,7 @@ jobs:
- name: Install QEMU to get dependencies
run: |
sudo apt update
sudo apt install -y qemu-system-arm
sudo apt install -y qemu-system-arm qemu-system-riscv32
sudo apt-get install git libglib2.0-dev libfdt-dev libpixman-1-dev zlib1g-dev ninja-build

- if: ${{ steps.cache-qemu.outputs.cache-hit != 'true' }}
Expand Down Expand Up @@ -226,9 +269,9 @@ jobs:
name: qemu
path: qemu.tar

# Verify the example output with run-pass tests
testexamples:
name: QEMU run
# Platform lm3s6965: verify the example output with run-pass tests
testexampleslm3s6965:
name: QEMU run (lm3s6965)
needs: buildqemu
runs-on: ubuntu-22.04
strategy:
Expand Down Expand Up @@ -283,7 +326,71 @@ jobs:
which qemu-system-riscv32

- name: Run-pass tests
run: cargo xtask --deny-warnings --backend ${{ matrix.backend }} qemu
run: cargo xtask --deny-warnings --platform lm3s6965 --backend ${{ matrix.backend }} qemu

# Platform hifive1: verify the example output with run-pass tests
testexampleshifive1:
name: QEMU run (hifive1)
AfoHT marked this conversation as resolved.
Show resolved Hide resolved
needs: buildqemu
runs-on: ubuntu-22.04
strategy:
matrix:
backend:
- riscv32-imc-clint
- riscv32-imac-clint
toolchain:
- stable
steps:
- name: Checkout
uses: actions/checkout@v4

- name: Install Rust ${{ matrix.toolchain }}
run: |
rustup set profile minimal
rustup override set ${{ matrix.toolchain }}

- name: Configure Rust target
run: |
rustup target add riscv32imac-unknown-none-elf
rustup target add riscv32imc-unknown-none-elf

- name: Add Rust component llvm-tools-preview
run: rustup component add llvm-tools-preview

# Use precompiled binutils
- name: Install cargo-binutils
uses: taiki-e/install-action@v2
with:
tool: cargo-binutils

- name: Cache Dependencies
uses: Swatinem/rust-cache@v2

- name: Install QEMU to get dependencies
run: |
sudo apt update
sudo apt install -y qemu-system-riscv32

- name: Download built QEMU
uses: actions/download-artifact@v4
with:
name: qemu

- name: Extract QEMU into local path
run: tar -xf qemu.tar -C /usr/local/bin

- name: Check which QEMU is used
run: |
which qemu-system-arm
which qemu-system-riscv32

- name: Run-pass tests
if: ${{ matrix.backend == 'riscv32-imc-clint' }}
run: cargo xtask --deny-warnings --platform hifive1 --backend ${{ matrix.backend }} --exampleexclude static qemu

- name: Run-pass tests
if: ${{ matrix.backend != 'riscv32-imc-clint' }}
run: cargo xtask --deny-warnings --platform hifive1 --backend ${{ matrix.backend }} qemu

# Run test suite
tests:
Expand Down Expand Up @@ -719,10 +826,14 @@ jobs:
if: github.event_name == 'push' && success()
needs:
- formatcheck
- check
- clippy
- checkexamples
- testexamples
- checklm3s6965
# checkhifive1 TODO
- clippylm3s6965
# clippyhifive1 TODO
- checkexampleslm3s6965
- checkexampleshifive1
- testexampleslm3s6965
- testexampleshifive1
- tests
- docs
- mdbook
Expand Down
3 changes: 3 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -6,3 +6,6 @@
Cargo.lock
*.hex
book-target/

.DS_Store
.vscode/
17 changes: 17 additions & 0 deletions ci/expected/hifive1/prio_inheritance.run
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
[Idle]: Started
[SoftMedium]: Started
[SoftMedium]: Shared: 1
[SoftHigh]: Started
[SoftHigh]: Shared: 2
[SoftHigh]: Finished
[SoftMedium]: Finished
[SoftLow1]: Started
[SoftLow1]: Shared: 3
[SoftLow1]: Yield
[SoftLow2]: Started
[SoftLow2]: Shared: 4
[SoftLow2]: Yield
[SoftLow1]: Finished
[SoftLow2]: Finished
[Idle]: Shared: 4
[Idle]: Finished
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
3 changes: 3 additions & 0 deletions ci/expected/lm3s6965/static.run
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
received message: 1
received message: 2
received message: 3
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
5 changes: 5 additions & 0 deletions ci/expected/lm3s6965/task.run
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
foo - start
foo - middle
baz
foo - end
bar
3 changes: 3 additions & 0 deletions ci/expected/lm3s6965/zero-prio-task.run
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
init
hello from async
hello from async2
11 changes: 11 additions & 0 deletions examples/hifive1/.cargo/config.toml
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
[target.'cfg(all(target_arch = "riscv32", target_os = "none"))']
runner = "qemu-system-riscv32 -machine sifive_e,revb=true -nographic -semihosting-config enable=on,target=native -kernel"
# runner = "riscv64-unknown-elf-gdb -q -x gdb_init"
rustflags = [
"-C", "link-arg=-Thifive1-link.x",
]

[build]
# Pick ONE of these compilation targets
# target = "riscv32imc-unknown-none-elf" # non-atomic support
target = "riscv32imac-unknown-none-elf" # atomic support (partial)
Loading