riscv: Support XUANTIE extended CSR save/restore during task switching

This patch focuses on two XUANTIE extended CSRs:
- FXCR[31]: Process 16-bit floating point numbers according to the BFloat
16 format.
- UTNMODE: FP8 output can be ovf or sat mode. Introduced by XUANTIE C908X.

When using, first enable CONFIG_XUANTIE_CSR_EXT, then set the 'riscv,isa'
fields of dts to dynamically control whether to save/restore the
corresponding CSR. For example, for FXCR, you need to add 'xtheadfxcr',
and for UTNMODE, you need to add 'xtheadutnmode'.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>

arch/riscv/Kconfig

@@ -726,9 +726,9 @@ config XUANTIE_CSR_EXT
 	default y
 	depends on FPU
 	help
-	  XUANTIE U-mode Extended Control and Status Register.
-
-	  If unsure, say N.
+	  This config enable XUANTIE U-mode Extended Control and Status Register.
+	  These CSRs may be set to different values ​​by the user in different processes, and 
+	  can be saved and restored when switching tasks in combination with dts.
 
 menu "Kernel features"
 

arch/riscv/include/asm/xuantie_csr_ext.h

@@ -35,4 +35,4 @@ static __always_inline bool has_xuantie_csr_ext(void) { return false; }
 #define __switch_to_xuantie_csr_ext(__prev, __next)	do {} while (0)
 
 #endif /* CONFIG_XUANTIE_CSR_EXT */
-#endif /* _ASM_XUANTIE_CSR_EXT_H */
+#endif /* _ASM_XUANTIE_CSR_EXT_H */