Remove comments

sarchlab · Dec 7, 2023 · 4537f39 · 4537f39
1 parent 654765d
commit 4537f39
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/timing/cu/computeunit.go b/timing/cu/computeunit.go
@@ -46,7 +46,6 @@ type ComputeUnit struct {
 	LDSUnit          SubComponent
 	SRegFile         RegisterFile
 	VRegFile         []RegisterFile
-	// VectorDecoder    SubComponent
 
 	InstMem          sim.Port
 	ScalarMem        sim.Port