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v1.1.0-pre.1

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@sarweiler sarweiler released this 01 Nov 17:14
· 7 commits to master since this release
v1.1.0-pre.1
90f62bf

This is a pre-release, meaning the PCB design for this version is untested and I haven't built this version yet. Once I have built and tested this version of the PCB I will release it as v1.1.0.

CHANGELOG:

  • move resisitors for left DB9 port to the right of the port
  • add 4mm mounting holes
  • pixel art without dithering
Assets 3
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