The Opensource Verilog Workbench

A Verilog workbench with opensource toolchains that lets you write and simulate your verilog code with ease

Table of Contents

1. About The Project
   • Built With
2. Getting Started
   • Prerequisites
   • Installation
3. Usage
4. License

About The Project

This project aims to ease the setup of your verilog projects by providing you with a precoded workbench.

Built With

• Icarus Verilog (iverilog) To simulate your verilog code
• Cocotb To verify your verilog code by writing python testbenches
• GTKWave To view the input or outpot waveforms of your design
• Yosys To synthesize your design into actual hardware and view it

Getting Started

To get a local copy up and running follow these simple steps.

Prerequisites

For the project to work you would have to install these things first:

• Icarus Verilog
• Cocotb
• GTKWave
• Yosys

Debian 12 Bookworm:

$ sudo apt install iverilog yosys gtkwave verilator imagemagick geeqie
# WARNING: Using "--break-system-packages" could break your system. it is recommended to use a python venv instead
$ pip install --break-system-packages cocotb
# make sure ~/.local/bin/ is in your PATH

Installation

1. Clone the repo

   git clone https://github.com/sfmth/verilog-workbench/ && cd verilog-workbench

Usage

To run a simulation, first you would have to write your verilog code and testbench. You can put your Verilog code in verilog-workbench/src/ and your test bench in verilog-workbench/test. Each verilog file should include only a single module and also the name of the file has to be the same as the module name. For cocotb python test benches it is mandatory to add test_ to the beginning of the module name and use it as the file name for the corresponding module. There is also a need to add a dump code snippet to the end of your module, you can find it in src/encoder.v.

Then, in order to run the simulation you can do:

make gtkwave NAM=<module name> SINGLE=<True / False>

And if you want to see your synthesized design you can do:

make show_synth_png NAM=<module name>

Or for a more detailed gate level synthesize you can run the following:

make show_synth_full_svg NAM=<module name>

License

Distributed under the MIT License. See LICENSE for more information.