Merge pull request #15 from sgherbst/zc706

Add support for ZC706 board
sgherbst · Jun 30, 2020 · fafaa08 · fafaa08
2 parents bad0f99 + c094d3e
commit fafaa08
Show file tree

Hide file tree

Showing 5 changed files with 34 additions and 3 deletions.
diff --git a/anasymod/config.py b/anasymod/config.py
@@ -100,6 +100,8 @@ def _fetch_board(self):
             return TE0720()
         elif self.cfg.board_name == BoardNames.ZC702:
             return ZC702()
+        elif self.cfg.board_name == BoardNames.ZC706:
+            return ZC706()
         elif self.cfg.board_name == BoardNames.ARTY_200T_CUSTOM_LIDAR:
             return ARTY_200T_CUSTOM_LIDAR()
         else:

diff --git a/anasymod/enums.py b/anasymod/enums.py
@@ -19,18 +19,20 @@ class BoardNames:
     ARTY_A7
     VC707
     ZC702
+    ZC706
     ULTRA96
     TE0720
+
     """
     PYNQ_Z1 = 'PYNQ_Z1'
     ARTY_A7 = 'ARTY_A7'
     VC707 = 'VC707'
     ZC702 = 'ZC702'
+    ZC706 = 'ZC706'
     ULTRA96 = 'ULTRA96'
     TE0720 = 'TE0720'
     ARTY_200T_CUSTOM_LIDAR = 'ARTY_200T_CUSTOM_LIDAR'
 
-
 class PortDir:
     """
     Container including enums for all supported port directions.

diff --git a/anasymod/fpga_boards/boards.py b/anasymod/fpga_boards/boards.py
@@ -88,4 +88,17 @@ class ULTRA96():
     board_part = None
     full_part_name = 'xczu3eg-sbva484-???'
     short_part_name = 'xczu3eg'
-    fpga_sim_ctrl = [FPGASimCtrl.UART_ZYNQ, FPGASimCtrl.VIVADO_VIO]
+    fpga_sim_ctrl = [FPGASimCtrl.UART_ZYNQ, FPGASimCtrl.VIVADO_VIO]
+
+class ZC706():
+    """
+    Container to store ZC706 FPGA board specific properties.
+    """
+    clk_pin = ['H9', 'G9']
+    clk_io = 'LVDS'
+    clk_freq = 200e6
+    board_part = 'xilinx.com:zc706:part0:1.4'
+    full_part_name = 'xc7z045ffg900-2'
+    short_part_name = 'xc7z045'
+    dbg_hub_clk_freq = 100e6
+    fpga_sim_ctrl = [FPGASimCtrl.UART_ZYNQ, FPGASimCtrl.VIVADO_VIO]
diff --git a/codecov.yml b/codecov.yml
@@ -0,0 +1,14 @@
+# configuration related to pull request comments
+comment: no # do not comment PR with the result
+
+coverage:
+  range: 50..90 # coverage lower than 50 is red, higher than 90 green, between color code
+
+  status:
+    project: # settings affecting project coverage
+      default:
+        target: auto # auto % coverage target
+        threshold: 5%  # allow for 5% reduction of coverage without failing
+
+    # do not run coverage on patch nor changes
+    patch: false
diff --git a/setup.py b/setup.py
@@ -2,7 +2,7 @@
 from setuptools import setup, find_packages
 
 name = 'anasymod'
-version = '0.2.9'
+version = '0.3.2'
 
 DESCRIPTION = '''\
 Tool for running mixed-signal emulations on FPGAs\