GitHub - shinawy/RISC-V-Processor: RISC-V processor on Nexys-A7 100T in verilog. Fully functional RISC-V architecture based pipelined processor using Verilog.

shinawy / RISC-V-Processor Public

RISC-V processor on Nexys-A7 100T in verilog. Fully functional RISC-V architecture based pipelined processor using Verilog.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
BinaryParsing		BinaryParsing
FPGA Project/project_ms3_new		FPGA Project/project_ms3_new
FillMem		FillMem
Screenshots		Screenshots
Simulation Project/MileStone 3		Simulation Project/MileStone 3
SourceFiles		SourceFiles
TestCases		TestCases
Datapath Architecture.pdf		Datapath Architecture.pdf
Milestone 3 Report.rtf		Milestone 3 Report.rtf
readme file.txt		readme file.txt