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FpgaExample: use new villas interface and make logging optional.
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Speeds up simulation by several orders of magnitude

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
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@n-eiling
n-eiling committed Jul 29, 2024
1 parent 2aae38b commit 71f1e9e
Showing 1 changed file with 48 additions and 28 deletions.
76 changes: 48 additions & 28 deletions dpsim-villas/examples/cxx/FpgaExample.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9,9 +9,11 @@
#include <fstream>

#include <DPsim.h>
#include <dpsim-models/Attribute.h>
#include <dpsim-models/DP/DP_Ph1_CurrentSource.h>
#include <dpsim-models/SimNode.h>
#include <dpsim-villas/InterfaceVillas.h>
#include <dpsim-villas/InterfaceVillasQueueless.h>
#include <dpsim/Utils.h>

using namespace DPsim;
Expand All @@ -21,11 +23,17 @@ using namespace CPS::DP::Ph1;
const std::string buildFpgaConfig(CommandLineArgs &args) {
std::filesystem::path fpgaIpPath =
"/usr/local/etc/villas/node/etc/fpga/vc707-xbar-pcie-dino/"
"vc707-xbar-pcie-dino.json";
"vc707-xbar-pcie-dino-v2.json";

if (args.options.find("ips") != args.options.end()) {
fpgaIpPath = std::filesystem::path(args.getOptionString("ips"));
}
std::string loopbackConfig = fmt::format(
R"STRING(
"queuelen": 1024,
"samplelen": 1024,
"mode": "polling"
)STRING");
std::string cardConfig = fmt::format(
R"STRING("card": {{
"interface": "pcie",
Expand All @@ -48,7 +56,8 @@ const std::string buildFpgaConfig(CommandLineArgs &args) {
"signals": [{{
"name": "from_dpsim",
"type": "complex",
"unit": "V"
"unit": "V",
"builtin": false
}}],
"hooks": [{{
"type": "dp",
Expand All @@ -63,12 +72,18 @@ const std::string buildFpgaConfig(CommandLineArgs &args) {
std::string signalInConfig = fmt::format(
R"STRING("in": {{
"signals": [{{
"name": "seqnum",
"type": "integer",
"unit": "",
"builtin": false
}},
{{
"name": "to_dpsim",
"type": "float",
"unit": "V",
"builtin": false
}}],
"hooks": ["print", {{
"hooks": [{{
"type": "dp",
"signal": "to_dpsim",
"f0": {},
Expand All @@ -91,37 +106,39 @@ const std::string buildFpgaConfig(CommandLineArgs &args) {
}

SystemTopology loopbackTopology(CommandLineArgs &args,
std::shared_ptr<InterfaceVillas> intf,
std::shared_ptr<Interface> intf,
std::shared_ptr<DataLogger> logger) {
// Nodes
auto n1 = SimNode::make("n1");

// Components
auto vs = VoltageSource::make("v_s");
vs->setParameters(Complex(10, 0), args.sysFreq);
vs->setParameters(Complex(10, 0), 0);
auto rl = Resistor::make("r_l");
rl->setParameters(1);

// Topology
vs->connect({SimNode::GND, n1});
vs->connect({n1, SimNode::GND});
rl->connect({n1, SimNode::GND});

// Interface
intf->importAttribute(vs->mVoltageRef, 0, false, false, "from_dino", "A");
intf->exportAttribute(n1->mVoltage->deriveCoeff<Complex>(0, 0), 0, true,
"to_dino", "V");
intf->printVillasSignals();
auto seqnumAttribute = CPS::AttributeStatic<Int>::make(0);
intf->addImport(seqnumAttribute, true, true);
intf->addImport(vs->mVoltageRef, true, true);
intf->addExport(n1->mVoltage->deriveCoeff<Complex>(0, 0));

// Logger
logger->logAttribute("v1", n1->mVoltage);
logger->logAttribute("rl_i", rl->mIntfCurrent);
if (logger) {
logger->logAttribute("v1", n1->mVoltage);
logger->logAttribute("rl_i", rl->mIntfCurrent);
}

return SystemTopology(args.sysFreq, SystemNodeList{SimNode::GND, n1},
SystemComponentList{vs, rl});
}

SystemTopology hilTopology(CommandLineArgs &args,
std::shared_ptr<InterfaceVillas> intf,
std::shared_ptr<Interface> intf,
std::shared_ptr<DataLogger> logger) {
// Nodes
auto n1 = SimNode::make("n1");
Expand All @@ -137,27 +154,26 @@ SystemTopology hilTopology(CommandLineArgs &args,
cs->setParameters(Complex(0, 0));

// Topology
vs->connect({SimNode::GND, n1});
rs->connect({n1, n2});
cs->connect({n2, SimNode::GND});

// Interface
intf->importAttribute(cs->mCurrentRef, 0, false, false, "from_dino", "A");
intf->exportAttribute(n2->mVoltage->deriveCoeff<Complex>(0, 0), 0, true,
"to_dino", "V");
intf->printVillasSignals();
auto seqnumAttribute = CPS::AttributeStatic<uint32_t>::make(0);
intf->addImport(seqnumAttribute, true, false);
intf->addImport(cs->mCurrentRef, true, false);
intf->addExport(n2->mVoltage->deriveCoeff<Complex>(0, 0));

// Logger
logger->logAttribute("v1", n1->mVoltage);
logger->logAttribute("v2", n2->mVoltage);
logger->logAttribute("cs_i", cs->mIntfCurrent);
if (logger) {
logger->logAttribute("v1", n1->mVoltage);
logger->logAttribute("v2", n2->mVoltage);
logger->logAttribute("cs_i", cs->mIntfCurrent);
}

return SystemTopology(args.sysFreq, SystemNodeList{SimNode::GND, n1, n2},
SystemComponentList{vs, rs, cs});
}

SystemTopology getTopology(CommandLineArgs &args,
std::shared_ptr<InterfaceVillas> intf,
std::shared_ptr<Interface> intf,
std::shared_ptr<DataLogger> logger) {
if (args.options.find("topology") != args.options.end()) {
std::string topology = args.getOptionString("topology");
Expand All @@ -174,17 +190,21 @@ int main(int argc, char *argv[]) {
CommandLineArgs args(argc, argv, "FpgaExample", 0.01, 10 * 60, 5.);
CPS::Logger::setLogDir("logs/" + args.name);

auto intf = std::make_shared<InterfaceVillas>(buildFpgaConfig(args));
auto intf = std::make_shared<InterfaceVillasQueueless>(
buildFpgaConfig(args), "FpgaExample", spdlog::level::off);
auto logger = DataLogger::make(args.name);

auto sys = getTopology(args, intf, logger);
auto sys = getTopology(args, intf, nullptr);

RealTimeSimulation sim(args.name, args);
Simulation sim(args.name, args);
sim.setSystem(sys);
sim.addInterface(intf);
sim.addLogger(logger);
//sim.addLogger(logger);
sim.run();

CPS::Logger::get("FpgaExample")->info("Simulation finished.");
sim.logStepTimes("FpgaExample");

//std::ofstream of("task_dependencies.svg");
//sim.dependencyGraph().render(of);
}

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