RISCy is a fully functional RISC-V CPU implemented from scratch using Logisim, a digital logic simulator. This project showcases the design and construction of a simplified RISC-V architecture, including essential components like the ALU, branch comparator, control logic, immediate generator, memory, partial load, partial store, and register file.
RISCy consists of the following key components:
ALU (Arithmetic Logic Unit): Performs arithmetic and logic operations.
Branch Comparator: Handles branch instructions and conditional jumps.
Control Logic: Manages the flow of instructions and control signals.
Immediate Generator: Generates immediate values for certain instruction types.
Memory: Stores data and instructions.
Partial Load and Store Units: Facilitate loading and storing of data from/to memory.
Register File: Stores and manages the CPU's registers.
![Screenshot 2023-09-18 at 3 24 41 PM](https://private-user-images.githubusercontent.com/55569594/268787901-aa1a69f0-f8e4-4812-8086-6b582c0797f3.png?jwt=eyJhbGciOiJIUzI1NiIsInR5cCI6IkpXVCJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3MjYwNDc5MzksIm5iZiI6MTcyNjA0NzYzOSwicGF0aCI6Ii81NTU2OTU5NC8yNjg3ODc5MDEtYWExYTY5ZjAtZjhlNC00ODEyLTgwODYtNmI1ODJjMDc5N2YzLnBuZz9YLUFtei1BbGdvcml0aG09QVdTNC1ITUFDLVNIQTI1NiZYLUFtei1DcmVkZW50aWFsPUFLSUFWQ09EWUxTQTUzUFFLNFpBJTJGMjAyNDA5MTElMkZ1cy1lYXN0LTElMkZzMyUyRmF3czRfcmVxdWVzdCZYLUFtei1EYXRlPTIwMjQwOTExVDA5NDAzOVomWC1BbXotRXhwaXJlcz0zMDAmWC1BbXotU2lnbmF0dXJlPWYyNzcwMTdjZTNmZmY3YjAwOGRmMDFkYzg3MmE5ODY2MjVkZWU2MzAxNzQ4MDY2YWU2MzRmZjA5OTcwNTJjNmEmWC1BbXotU2lnbmVkSGVhZGVycz1ob3N0JmFjdG9yX2lkPTAma2V5X2lkPTAmcmVwb19pZD0wIn0.etV10pMP8rx2aSusZE7IDmpBNhXVqhU-mpP88ELQB4k)