RISCy is a fully functional RISC-V CPU implemented from scratch using Logisim, a digital logic simulator. This project showcases the design and construction of a simplified RISC-V architecture, including essential components like the ALU, branch comparator, control logic, immediate generator, memory, partial load, partial store, and register file.
RISCy consists of the following key components:
ALU (Arithmetic Logic Unit): Performs arithmetic and logic operations.
Branch Comparator: Handles branch instructions and conditional jumps.
Control Logic: Manages the flow of instructions and control signals.
Immediate Generator: Generates immediate values for certain instruction types.
Memory: Stores data and instructions.
Partial Load and Store Units: Facilitate loading and storing of data from/to memory.
Register File: Stores and manages the CPU's registers.
Figure above shows cpu.circ and its interaction with each clock cycle