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beeb

BBC Micro Model B/Master core

This is a port of Mike Sterlings great BBC Micro on FPGA with major changes by Stephen Leary, David Banks and others.

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DemiSTify'ed BBC micro

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  • VHDL 62.7%
  • Verilog 26.9%
  • SystemVerilog 3.6%
  • Tcl 3.1%
  • C++ 2.5%
  • Shell 0.5%
  • Other 0.7%