I've been working on NVC, a Free Software VHDL compiler and simulator, in my spare time for the last 10 years. Recently I've made a lot of progress adding support for VHDL-2008 language features and I've got big plans for the future including VHDL-2019, multi-threaded simulation, and Verilog/mixed-language support. If you'd like to support my work please consider donating a few dollars a month. Thank you!