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Make use of properties consistent
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nalu-svk authored and leifwar committed Feb 21, 2022
1 parent 33fef5c commit f026f9a
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Showing 2 changed files with 14 additions and 13 deletions.
8 changes: 6 additions & 2 deletions cimsparql/parse_xml.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
import collections
import gzip
import re
from functools import cached_property
from pathlib import Path
from typing import Callable, Dict, Iterable, List, Optional, Tuple, Union
from zipfile import ZipFile
Expand Down Expand Up @@ -319,20 +320,23 @@ def __str__(self) -> str:
file_desc = ", ".join([f"{profile}: {path.stem}" for profile, path in self.paths.items()])
return f"<SvTpCimXml object, {file_desc}>"

@property
@cached_property
def voltage(self) -> pd.DataFrame:
return self._parser["sv"].parse("SvVoltage").set_index("mrid")

@property
@cached_property
def tap_steps(self) -> pd.DataFrame:
return self._parser["sv"].parse("SvTapStep").set_index("mrid")

@cached_property
def bus_data(self, *args, **kwargs) -> pd.DataFrame:
return self._parser["tp"].parse("TopologicalNode").set_index("mrid")

@cached_property
def terminal(self, *args, **kwargs) -> pd.DataFrame:
return self._parser["tp"].parse("Terminal").set_index("mrid")

@cached_property
def powerflow(self, *args, **kwargs) -> pd.DataFrame:
return self._parser["sv"].parse("SvPowerFlow").set_index("mrid")

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19 changes: 8 additions & 11 deletions tests/test_parse_xml.py
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ def sv_tp_cim(profiles: List[str]) -> SvTpCimXml:

@pytest.fixture(scope="module")
def bus_data(sv_tp_cim) -> pd.DataFrame:
return sv_tp_cim.bus_data()
return sv_tp_cim.bus_data


@pytest.fixture(scope="module")
Expand All @@ -57,25 +57,22 @@ def test_parse_sv_tp_cim_xml_bus_data(bus_data: pd.DataFrame):


def test_parse_sv_tp_cim_xml_terminal(sv_tp_cim: SvTpCimXml):
assert sv_tp_cim.terminal().shape == (4, 2)
assert sv_tp_cim.terminal.shape == (4, 2)


def test_parse_sv_tp_cim_xml_powerflow(sv_tp_cim: SvTpCimXml):
powerflow = sv_tp_cim.powerflow()
assert powerflow.shape == (4, 2)
assert (powerflow.dtypes == float).all()
assert sv_tp_cim.powerflow.shape == (4, 2)
assert (sv_tp_cim.powerflow.dtypes == float).all()


def test_parse_sv_tp_cim_xml_voltage(sv_tp_cim: SvTpCimXml):
voltage = sv_tp_cim.voltage
assert voltage.shape == (4, 2)
assert (voltage.dtypes == float).all()
assert sv_tp_cim.voltage.shape == (4, 2)
assert (sv_tp_cim.voltage.dtypes == float).all()


def test_parse_sv_tp_cim_xml_tap_step(sv_tp_cim: SvTpCimXml):
tap_steps = sv_tp_cim.tap_steps
assert tap_steps.shape == (4, 1)
assert (tap_steps.dtypes == int).all()
assert sv_tp_cim.tap_steps.shape == (4, 1)
assert (sv_tp_cim.tap_steps.dtypes == int).all()


def test_parse_cim_file():
Expand Down

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