put whole design in reset

stevej · Oct 25, 2024 · f3e229f · f3e229f
1 parent 8c0ea83
commit f3e229f
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/test/test.py b/test/test.py
@@ -18,6 +18,8 @@ async def test_rms_five_high_for_reset(dut):
         dut.ena.value = 1
         dut.ui_in.value = 0
         dut.uio_in.value = 0
+        dut.rst_n.value = 1
+        await ClockCycles(dut.clk, 1)
         dut.rst_n.value = 0
         await ClockCycles(dut.clk, 1)
         dut.rst_n.value = 1