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Merge pull request #1420 from d4ilyrun/g0/erase_bank2
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[STM32Gx]: Added erase support for multi-bank products
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Nightwalker-87 authored Aug 11, 2024
2 parents 07f3118 + bff6151 commit 1f0b95c
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1 change: 1 addition & 0 deletions inc/stm32flash.h
Original file line number Diff line number Diff line change
Expand Up @@ -181,6 +181,7 @@
#define FLASH_Gx_CR_PNB (3) /* Page number */
#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */
#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */
#define FLASH_Gx_CR_BKER (13) /* Bank selection for erase operation */
#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/
#define FLASH_Gx_CR_STRT (16) /* Start */
#define FLASH_Gx_CR_OPTSTRT (17) /* Start of modification of option bytes */
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12 changes: 12 additions & 0 deletions src/stlink-lib/common_flash.c
Original file line number Diff line number Diff line change
Expand Up @@ -1122,6 +1122,18 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
stlink_read_debug32(sl, FLASH_Gx_CR, &val);
// sec 3.7.5 - PNB[9:0] is offset by 3. PER is 0x2.
val &= ~(0x7FF << 3);
// sec 3.3.8 - Error PGSERR
// * In the page erase sequence: PG, FSTPG and MER1 are not cleared when PER is set
val &= ~(1 << FLASH_Gx_CR_MER1 | 1 << FLASH_Gx_CR_MER2);
val &= ~(1 << FLASH_Gx_CR_PG);
// Products of the Gx series with more than 128K of flash use 2 banks.
// In this case we need to specify which bank to erase (sec 3.7.5 - BKER)
if (sl->flash_size > (128 * 1024) &&
((flashaddr - STM32_FLASH_BASE) >= sl->flash_size / 2)) {
val |= (1 << FLASH_Gx_CR_BKER); // erase bank 2
} else {
val &= ~(1 << FLASH_Gx_CR_BKER); // erase bank 1
}
val |= ((flash_page & 0x7FF) << 3) | (1 << FLASH_CR_PER);
stlink_write_debug32(sl, FLASH_Gx_CR, val);
// STM32L5x2xx has two banks with 2k pages or single with 4k pages
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