finishing touches

crates/core/executor/src/executor.rs

@@ -666,7 +666,7 @@ impl<'a> Executor<'a> {
         emit_cpu_dependencies(self, self.record.cpu_events.len() - 1);
     }
 
-    /// Emit an ALU event.
+    /// Emit an instruction event.
     fn emit_instruction(&mut self, opcode: Opcode, a: u32, b: u32, c: u32, lookup_id: LookupId) {
         let event = InstrEvent {
             lookup_id,

crates/core/executor/src/record.rs

@@ -160,7 +160,6 @@ impl ExecutionRecord {
         }
     }
 
-    /// Take out events from the [`ExecutionRecord`] that should be deferred to a separate shard.
     /// Take out events from the [`ExecutionRecord`] that should be deferred to a separate shard.
     ///
     /// Note: we usually defer events that would increase the recursion cost significantly if

crates/core/machine/src/alu/add_sub/mod.rs

@@ -182,9 +182,10 @@ where
         let is_real = local.is_add + local.is_sub;
 
         // Calculate the opcode.
-        // local.is_add == 1 -> opcode == 0
-        // local.is_sub == 1 -> opcode == 1
-        // We also constrain the local.is_add and local.is_sub are bool and never both true.
+        // For add instruction, we should set Opcode == 0.
+        // For sub instruction, we should set Opcode == 1.
+        // We can simply set opcode = local.is_sub since local.is_add and local.is_sub are
+        // contraints to be bool and mutually exclusive.
         let opcode = local.is_sub;
 
         // Constrain the incrementing nonce.

crates/core/machine/src/cpu/air/mod.rs

@@ -307,12 +307,13 @@ impl CpuChip {
                 - (is_branch_instruction
                     + local.selectors.is_jal
                     + local.selectors.is_jalr
+                    + local.selectors.is_alu
                     + is_halt),
         );
 
-        // Verify that the pc increments by 4 for all instructions except branch, jump and halt
-        // instructions. The other case is handled by eval_jump, eval_branch and eval_ecall
-        // (for halt).
+        // Verify that the pc increments by 4 for all instructions except branch, jump, halt, and
+        // ALU instructions. The other case is handled by eval_jump, eval_branch, eval_ecall
+        // (for halt), and the ALU specific tables.
         builder
             .when_transition()
             .when(next.is_real)

crates/core/machine/src/cpu/trace.rs

@@ -191,7 +191,10 @@ impl CpuChip {
         let is_halt = self.populate_ecall(cols, event, nonce_lookup);
 
         cols.is_sequential_instr = F::from_bool(
-            !instruction.is_branch_instruction() && !instruction.is_jump_instruction() && !is_halt,
+            !instruction.is_branch_instruction()
+                && !instruction.is_jump_instruction()
+                && !is_halt
+                && !instruction.is_alu_instruction(),
         );
 
         // Assert that the instruction is not a no-op.