checkpoint

crates/core/executor/src/events/memory.rs

@@ -232,3 +232,12 @@ pub struct MemoryLocalEvent {
     /// The final memory access.
     pub final_mem_access: MemoryRecord,
 }
+
+/// Memory Instructions Event.
+///
+/// This object encapsulates the information needed to prove a memory instruction operation.
+#[derive(Debug, Clone, Serialize, Deserialize)]
+pub struct MemoryInstructionsEvent {
+    /// The address.
+    pub addr: u32,
+}

crates/core/executor/src/record.rs

@@ -13,8 +13,8 @@ use super::{program::Program, Opcode};
 use crate::{
     events::{
         add_sharded_byte_lookup_events, AluEvent, ByteLookupEvent, ByteRecord, CpuEvent, LookupId,
-        MemoryInitializeFinalizeEvent, MemoryLocalEvent, MemoryRecordEnum, PrecompileEvent,
-        PrecompileEvents, SyscallEvent,
+        MemoryInitializeFinalizeEvent, MemoryInstructionsEvent, MemoryLocalEvent, MemoryRecordEnum,
+        PrecompileEvent, PrecompileEvents, SyscallEvent,
     },
     syscalls::SyscallCode,
     CoreShape,
@@ -45,6 +45,8 @@ pub struct ExecutionRecord {
     pub divrem_events: Vec<AluEvent>,
     /// A trace of the SLT, SLTI, SLTU, and SLTIU events.
     pub lt_events: Vec<AluEvent>,
+    /// A trace of the memory instructions.
+    pub memory_instructions_events: Vec<MemoryInstructionsEvent>,
     /// A trace of the byte lookups that are needed.
     pub byte_lookups: HashMap<u32, HashMap<ByteLookupEvent, usize>>,
     /// A trace of the precompile events.
@@ -80,6 +82,7 @@ impl Default for ExecutionRecord {
             shift_right_events: Vec::default(),
             divrem_events: Vec::default(),
             lt_events: Vec::default(),
+            memory_instructions_events: Vec::default(),
             byte_lookups: HashMap::default(),
             precompile_events: PrecompileEvents::default(),
             global_memory_initialize_events: Vec::default(),
@@ -161,6 +164,15 @@ impl ExecutionRecord {
         }
     }
 
+    /// Add a memory instructions event to the execution record.
+    pub fn add_memory_instructions_event(
+        &mut self,
+        memory_instructions_event: MemoryInstructionsEvent,
+    ) {
+        self.memory_instructions_events.push(memory_instructions_event);
+    }
+
+    /// Take out events from the [`ExecutionRecord`] that should be deferred to a separate shard.
     /// Take out events from the [`ExecutionRecord`] that should be deferred to a separate shard.
     ///
     /// Note: we usually defer events that would increase the recursion cost significantly if
@@ -331,6 +343,10 @@ impl MachineRecord for ExecutionRecord {
         stats.insert("shift_right_events".to_string(), self.shift_right_events.len());
         stats.insert("divrem_events".to_string(), self.divrem_events.len());
         stats.insert("lt_events".to_string(), self.lt_events.len());
+        stats.insert(
+            "memory_instructions_events".to_string(),
+            self.memory_instructions_events.len(),
+        );
 
         for (syscall_code, events) in self.precompile_events.iter() {
             stats.insert(format!("syscall {syscall_code:?}"), events.len());
@@ -367,6 +383,7 @@ impl MachineRecord for ExecutionRecord {
         self.shift_right_events.append(&mut other.shift_right_events);
         self.divrem_events.append(&mut other.divrem_events);
         self.lt_events.append(&mut other.lt_events);
+        self.memory_instructions_events.append(&mut other.memory_instructions_events);
         self.syscall_events.append(&mut other.syscall_events);
 
         self.precompile_events.append(&mut other.precompile_events);

crates/core/machine/src/alu/add_sub/mod.rs

@@ -193,7 +193,7 @@ where
 
         // Receive the arguments.  There are separate receives for ADD and SUB.
         // For add, `add_operation.value` is `a`, `operand_1` is `b`, and `operand_2` is `c`.
-        builder.receive_alu(
+        builder.receive_instruction(
             Opcode::ADD.as_field::<AB::F>(),
             local.add_operation.value,
             local.operand_1,
@@ -204,7 +204,7 @@ where
         );
 
         // For sub, `operand_1` is `a`, `add_operation.value` is `b`, and `operand_2` is `c`.
-        builder.receive_alu(
+        builder.receive_instruction(
             Opcode::SUB.as_field::<AB::F>(),
             local.operand_1,
             local.add_operation.value,

crates/core/machine/src/alu/bitwise/mod.rs

@@ -205,7 +205,7 @@ where
             + local.is_and * Opcode::AND.as_field::<AB::F>();
 
         // Receive the arguments.
-        builder.receive_alu(
+        builder.receive_instruction(
             cpu_opcode,
             local.a,
             local.b,

crates/core/machine/src/alu/divrem/mod.rs

@@ -496,7 +496,7 @@ where
             ];
 
             // The lower 4 bytes of c_times_quotient must match the lower 4 bytes of (c * quotient).
-            builder.send_alu(
+            builder.send_instruction(
                 AB::Expr::from_canonical_u32(Opcode::MUL as u32),
                 Word(lower_half),
                 local.quotient,
@@ -521,7 +521,7 @@ where
                 local.c_times_quotient[7].into(),
             ];
 
-            builder.send_alu(
+            builder.send_instruction(
                 opcode_for_upper_half,
                 Word(upper_half),
                 local.quotient,
@@ -679,7 +679,7 @@ where
             }
             // In the case that `c` or `rem` is negative, instead check that their sum is zero by
             // sending an AddEvent.
-            builder.send_alu(
+            builder.send_instruction(
                 AB::Expr::from_canonical_u32(Opcode::ADD as u32),
                 Word([zero.clone(), zero.clone(), zero.clone(), zero.clone()]),
                 local.c,
@@ -688,7 +688,7 @@ where
                 local.abs_c_alu_event_nonce,
                 local.abs_c_alu_event,
             );
-            builder.send_alu(
+            builder.send_instruction(
                 AB::Expr::from_canonical_u32(Opcode::ADD as u32),
                 Word([zero.clone(), zero.clone(), zero.clone(), zero.clone()]),
                 local.remainder,
@@ -734,7 +734,7 @@ where
 
             // Dispatch abs(remainder) < max(abs(c), 1), this is equivalent to abs(remainder) <
             // abs(c) if not division by 0.
-            builder.send_alu(
+            builder.send_instruction(
                 AB::Expr::from_canonical_u32(Opcode::SLTU as u32),
                 Word([one.clone(), zero.clone(), zero.clone(), zero.clone()]),
                 local.abs_remainder,
@@ -816,7 +816,7 @@ where
                     + local.is_rem * rem
             };
 
-            builder.receive_alu(
+            builder.receive_instruction(
                 opcode,
                 local.a,
                 local.b,

crates/core/machine/src/alu/lt/mod.rs

@@ -441,7 +441,7 @@ where
         builder.assert_bool(local.is_slt + local.is_sltu);
 
         // Receive the arguments.
-        builder.receive_alu(
+        builder.receive_instruction(
             local.is_slt * AB::F::from_canonical_u32(Opcode::SLT as u32)
                 + local.is_sltu * AB::F::from_canonical_u32(Opcode::SLTU as u32),
             local.a,

crates/core/machine/src/alu/mul/mod.rs

@@ -441,7 +441,7 @@ where
         }
 
         // Receive the arguments.
-        builder.receive_alu(
+        builder.receive_instruction(
             opcode,
             local.a,
             local.b,

crates/core/machine/src/alu/sll/mod.rs

@@ -386,7 +386,7 @@ where
         builder.assert_bool(local.is_real);
 
         // Receive the arguments.
-        builder.receive_alu(
+        builder.receive_instruction(
             AB::F::from_canonical_u32(Opcode::SLL as u32),
             local.a,
             local.b,

crates/core/machine/src/alu/sr/mod.rs

@@ -506,7 +506,7 @@ where
         builder.assert_eq(local.is_srl + local.is_sra, local.is_real);
 
         // Receive the arguments.
-        builder.receive_alu(
+        builder.receive_instruction(
             local.is_srl * AB::F::from_canonical_u32(Opcode::SRL as u32)
                 + local.is_sra * AB::F::from_canonical_u32(Opcode::SRA as u32),
             local.a,

crates/core/machine/src/cpu/air/branch.rs

@@ -82,7 +82,7 @@ impl CpuChip {
             );
 
             // When we are branching, calculate branch_cols.next_pc <==> branch_cols.pc + c.
-            builder.send_alu(
+            builder.send_instruction(
                 Opcode::ADD.as_field::<AB::F>(),
                 branch_cols.next_pc,
                 branch_cols.pc,
@@ -177,7 +177,7 @@ impl CpuChip {
 
         // Calculate a_lt_b <==> a < b (using appropriate signedness).
         let use_signed_comparison = local.selectors.is_blt + local.selectors.is_bge;
-        builder.send_alu(
+        builder.send_instruction(
             use_signed_comparison.clone() * Opcode::SLT.as_field::<AB::F>()
                 + (AB::Expr::one() - use_signed_comparison.clone())
                     * Opcode::SLTU.as_field::<AB::F>(),
@@ -190,7 +190,7 @@ impl CpuChip {
         );
 
         // Calculate a_gt_b <==> a > b (using appropriate signedness).
-        builder.send_alu(
+        builder.send_instruction(
             use_signed_comparison.clone() * Opcode::SLT.as_field::<AB::F>()
                 + (AB::Expr::one() - use_signed_comparison) * Opcode::SLTU.as_field::<AB::F>(),
             Word::extend_var::<AB>(branch_cols.a_gt_b),

crates/core/machine/src/cpu/air/mod.rs

@@ -1,6 +1,5 @@
 pub mod branch;
 pub mod ecall;
-pub mod memory;
 pub mod register;
 
 use core::borrow::Borrow;
@@ -47,20 +46,14 @@ where
         );
 
         // Compute some flags for which type of instruction we are dealing with.
-        let is_memory_instruction: AB::Expr = self.is_memory_instruction::<AB>(&local.selectors);
         let is_branch_instruction: AB::Expr = self.is_branch_instruction::<AB>(&local.selectors);
         let is_alu_instruction: AB::Expr = self.is_alu_instruction::<AB>(&local.selectors);
 
         // Register constraints.
         self.eval_registers::<AB>(builder, local, is_branch_instruction.clone());
 
-        // Memory instructions.
-        self.eval_memory_address_and_access::<AB>(builder, local, is_memory_instruction.clone());
-        self.eval_memory_load::<AB>(builder, local);
-        self.eval_memory_store::<AB>(builder, local);
-
         // ALU instructions.
-        builder.send_alu(
+        builder.send_instruction(
             local.instruction.opcode,
             local.op_a_val(),
             local.op_b_val(),
@@ -190,7 +183,7 @@ impl CpuChip {
         );
 
         // Verify that the new pc is calculated correctly for JAL instructions.
-        builder.send_alu(
+        builder.send_instruction(
             AB::Expr::from_canonical_u32(Opcode::ADD as u32),
             jump_columns.next_pc,
             jump_columns.pc,
@@ -201,7 +194,7 @@ impl CpuChip {
         );
 
         // Verify that the new pc is calculated correctly for JALR instructions.
-        builder.send_alu(
+        builder.send_instruction(
             AB::Expr::from_canonical_u32(Opcode::ADD as u32),
             jump_columns.next_pc,
             local.op_b_val(),
@@ -229,7 +222,7 @@ impl CpuChip {
         );
 
         // Verify that op_a == pc + op_b.
-        builder.send_alu(
+        builder.send_instruction(
             AB::Expr::from_canonical_u32(Opcode::ADD as u32),
             local.op_a_val(),
             auipc_columns.pc,

crates/core/machine/src/cpu/columns/mod.rs

@@ -3,7 +3,6 @@ mod branch;
 mod ecall;
 mod instruction;
 mod jump;
-mod memory;
 mod opcode;
 mod opcode_specific;
 
@@ -12,7 +11,6 @@ pub use branch::*;
 pub use ecall::*;
 pub use instruction::*;
 pub use jump::*;
-pub use memory::*;
 pub use opcode::*;
 pub use opcode_specific::*;
 

crates/core/machine/src/cpu/columns/opcode_specific.rs

@@ -1,4 +1,4 @@
-use crate::cpu::columns::{AuipcCols, BranchCols, JumpCols, MemoryColumns};
+use crate::cpu::columns::{AuipcCols, BranchCols, JumpCols};
 use std::{
     fmt::{Debug, Formatter},
     mem::{size_of, transmute},
@@ -14,7 +14,6 @@ pub const NUM_OPCODE_SPECIFIC_COLS: usize = size_of::<OpcodeSpecificCols<u8>>();
 #[derive(Clone, Copy)]
 #[repr(C)]
 pub union OpcodeSpecificCols<T: Copy> {
-    memory: MemoryColumns<T>,
     branch: BranchCols<T>,
     jump: JumpCols<T>,
     auipc: AuipcCols<T>,
@@ -24,9 +23,9 @@ pub union OpcodeSpecificCols<T: Copy> {
 impl<T: Copy + Default> Default for OpcodeSpecificCols<T> {
     fn default() -> Self {
         // We must use the largest field to avoid uninitialized padding bytes.
-        const_assert!(size_of::<MemoryColumns<u8>>() == size_of::<OpcodeSpecificCols<u8>>());
+        const_assert!(size_of::<JumpCols<u8>>() == size_of::<OpcodeSpecificCols<u8>>());
 
-        OpcodeSpecificCols { memory: MemoryColumns::default() }
+        OpcodeSpecificCols { jump: JumpCols::default() }
     }
 }
 
@@ -40,12 +39,6 @@ impl<T: Copy + Debug> Debug for OpcodeSpecificCols<T> {
 
 // SAFETY: Each view is a valid interpretation of the underlying array.
 impl<T: Copy> OpcodeSpecificCols<T> {
-    pub fn memory(&self) -> &MemoryColumns<T> {
-        unsafe { &self.memory }
-    }
-    pub fn memory_mut(&mut self) -> &mut MemoryColumns<T> {
-        unsafe { &mut self.memory }
-    }
     pub fn branch(&self) -> &BranchCols<T> {
         unsafe { &self.branch }
     }