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Update README with full F Extension Support
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visitorckw committed Nov 10, 2023
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5 changes: 2 additions & 3 deletions README.md
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Expand Up @@ -24,8 +24,7 @@ a focus on efficiency and readability.

Features:
* Fast interpreter for executing the RV32 ISA
* Comprehensive support for RV32I and M, A, C extensions
* Partial support for the F extension
* Comprehensive support for RV32I and M, A, C, F extensions
* Memory-efficient design
* Built-in ELF loader
* Implementation of commonly used newlib system calls
Expand Down Expand Up @@ -85,6 +84,7 @@ After the image is built, you can create a docker container by executing `docker
* `ENABLE_Zifencei`: Instruction-Fetch Fence
* `ENABLE_GDBSTUB` : GDB remote debugging support
* `ENABLE_SDL` : Experimental Display and Event System Calls
* `ENABLE_SOFTFLOAT` : SoftFloat implementation for F extension

e.g., run `make ENABLE_EXT_F=0` for the build without floating-point support.

Expand Down Expand Up @@ -143,7 +143,6 @@ Current progress of this emulator in riscv-arch-test (RV32):
- `C`: Standard Extension for Compressed Instruction
- `Zifencei`: Instruction-Fetch Fence
- `privilege`: RISCV Privileged Specification
* Unsupported tests (runnable but incomplete)
- `F` Standard Extension for Single-Precision Floating-Point

Detail in riscv-arch-test:
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1 comment on commit 311a100

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@jserv jserv commented on 311a100 Nov 10, 2023

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Benchmarks

Benchmark suite Current: 311a100 Previous: f18fed7 Ratio
Dhrystone 1485.85 Average DMIPS over 10 runs 1557 Average DMIPS over 10 runs 1.05
Coremark 1124.118 Average iterations/sec over 10 runs 1144.623 Average iterations/sec over 10 runs 1.02

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