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EA999 - 1st Semester of 2018 - UNICAMP

  • Learn VHDL concepts;
  • Develop VHDL programming skills;
  • Develop a Audio Synthesizer as a final project;

PROJECT

  • Milestone 1: Analog Audio Loop

    • Check if I2C interface is working properly, setting up WM8731.
  • Milestone 2: Digital Audio Loop

    • Check if I2S interface is being correctly implemented, using a sampling rate of 48kHz
  • Milestone 3: Implement a DDS

    • Generate a sine signal: using a LookUp Table and Low Pass Filter
  • Extras:

    • Proposed to implement a guitar tuner feature.
    • More.. if I have time

:)

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