tools: topology1: imx8ulp: change protocol and BCLK polarity

The BT codec used by the IW416 chip expects FSYNC to be
asserted for only one BCLK. Also, FSYNC should be active HIGH.
As such, change from I2S protocol to DSP_A protocol since the
configurations made for this protocol inside the SAI driver
are more suited.

Also, by default, the BT codec drives data on BCLK rising
edge and samples it on falling edge. With the DSP_A protocol,
the SAI driver also has the same configuration, which is wrong
since we can't drive and sample on the same edge and cycle. As such,
invert BCLK polarity such that the SAI will drive on rising edge
and sample on falling edge.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

tools/topology/topology1/sof-imx8ulp-9x9-btsco.m4

@@ -88,8 +88,8 @@ PCM_DUPLEX_ADD(Port0, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
 #		Freq(BCLK) = 16k * 16 * 1 = 256000
 dnl DAI_CONFIG(type, idx, link_id, name, sai_config)
 DAI_CONFIG(SAI, 6, 0, sai6-bt-sco-pcm-wb,
-	SAI_CONFIG(I2S, SAI_CLOCK(mclk, 12288000, codec_mclk_out),
-		SAI_CLOCK(bclk, `eval(FSYNC_RATE * 16)', codec_consumer),
+	SAI_CONFIG(DSP_A, SAI_CLOCK(mclk, 12288000, codec_mclk_out),
+		SAI_CLOCK(bclk, `eval(FSYNC_RATE * 16)', codec_consumer, inverted),
 		SAI_CLOCK(fsync, `FSYNC_RATE', codec_consumer),
 		SAI_TDM(1, 16, 1, 1),
 		SAI_CONFIG_DATA(SAI, 6, 0)))

tools/topology/topology1/sof-imx8ulp-btsco.m4

@@ -89,8 +89,8 @@ PCM_DUPLEX_ADD(Port0, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
 #		Freq(BCLK) = 16k * 16 * 1 = 256000
 dnl DAI_CONFIG(type, idx, link_id, name, sai_config)
 DAI_CONFIG(SAI, 5, 0, sai5-bt-sco-pcm-wb,
-	SAI_CONFIG(I2S, SAI_CLOCK(mclk, 12288000, codec_mclk_out),
-		SAI_CLOCK(bclk, `eval(FSYNC_RATE * 16)', codec_consumer),
+	SAI_CONFIG(DSP_A, SAI_CLOCK(mclk, 12288000, codec_mclk_out),
+		SAI_CLOCK(bclk, `eval(FSYNC_RATE * 16)', codec_consumer, inverted),
 		SAI_CLOCK(fsync, `FSYNC_RATE', codec_consumer),
 		SAI_TDM(1, 16, 1, 1),
 		SAI_CONFIG_DATA(SAI, 5, 0)))