audio: base_fw: refactor memory power management register access

This commit refactors the memory power management register access to use the HPSRAM_REGS and LPSRAM_REGS macros instead of direct io_reg_read calls. Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
thesofproject · Apr 11, 2024 · 749e8a4 · 749e8a4
1 parent fc49de7
commit 749e8a4
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Showing 6 changed files with 11 additions and 36 deletions.
diff --git a/src/audio/base_fw.c b/src/audio/base_fw.c
@@ -22,6 +22,7 @@
 #include <zephyr/drivers/counter.h>
 #endif
 #include <zephyr/logging/log_ctrl.h>
+#include <adsp_memory.h>
 
 /* TODO: Remove platform-specific code, see https://github.com/thesofproject/sof/issues/7549 */
 #if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) || defined(CONFIG_INTEL_ADSP_CAVS)
@@ -194,7 +195,7 @@ static int basefw_mem_state_info(uint32_t *data_offset, char *data)
 	tuple_data[index++] = info.ebb_state_dword_count;
 	for (i = 0; i < info.ebb_state_dword_count; i++) {
 #ifdef INTEL_ADSP
-		tuple_data[index + i] = io_reg_read(SHIM_HSPGCTL(i));
+		tuple_data[index + i] = HPSRAM_REGS(i)->HSxPGCTL;
 #else
 		tuple_data[index + i] = 0;
 #endif
@@ -222,11 +223,13 @@ static int basefw_mem_state_info(uint32_t *data_offset, char *data)
 	index = 0;
 	tuple_data[index++] = info.free_phys_mem_pages;
 	tuple_data[index++] = info.ebb_state_dword_count;
+	for (i = 0; i < info.ebb_state_dword_count; i++) {
 #ifdef INTEL_ADSP
-	tuple_data[index++] = io_reg_read(LSPGCTL);
+		tuple_data[index + i] = LPSRAM_REGS(i)->USxPGCTL;
 #else
-	tuple_data[index++] = 0;
+		tuple_data[index + i] = 0;
 #endif
+	}
 	tuple_data[index++] = info.page_alloc_struct.page_alloc_count;
 	ptr = (uint16_t *)(tuple_data + index);
 	for (i = 0; i < info.page_alloc_struct.page_alloc_count; i++)

diff --git a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h b/src/platform/intel/cavs/include/cavs/lib/pm_memory.h
@@ -22,6 +22,7 @@
 #include <sof/lib/shim.h>
 #include <rtos/wait.h>
 #include <sof/math/numbers.h>
+#include <adsp_memory.h>
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -72,14 +73,14 @@ static inline void cavs_pm_memory_hp_sram_mask_set(uint32_t mask, int segment,
 	uint32_t delay = 0;
 	uint32_t i;
 
-	io_reg_update_bits(SHIM_HSPGCTL(segment), mask, enabled ? 0 : mask);
-	io_reg_update_bits(SHIM_HSRMCTL(segment), mask, enabled ? 0 : mask);
+	io_reg_update_bits(&HPSRAM_REGS(segment)->HSxPGCTL, mask, enabled ? 0 : mask);
+	io_reg_update_bits(&HPSRAM_REGS(segment)->HSxRMCTL, mask, enabled ? 0 : mask);
 
 	/* Double check of PG status needed to confirm EBB readiness */
 	for (i = 0; i < 2; i++) {
 		idelay(MEMORY_POWER_CHANGE_DELAY);
 
-		while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected) {
+		while ((io_reg_read(&HPSRAM_REGS(segment)->HSxPGISTS) & mask) != expected) {
 			idelay(MEMORY_POWER_CHANGE_DELAY);
 			delay += MEMORY_POWER_CHANGE_DELAY;
 			if (delay >= MEMORY_POWER_CHANGE_TIMEOUT)

diff --git a/src/platform/lunarlake/include/platform/lib/shim.h b/src/platform/lunarlake/include/platform/lib/shim.h
@@ -44,11 +44,6 @@
 /** \brief LP RING Oscillator Clock Status */
 #define SHIM_CLKSTS_LROSCCS		BIT(29)
 
-#define L2HSBPM(x)			(0x17A800 + 0x0008 * (x))
-#define SHIM_HSPGCTL(x)			(L2HSBPM(x) + 0x0000)
-
-#define LSPGCTL				0x71D80
-
 #endif /* __PLATFORM_LIB_SHIM_H__ */
 
 #else

diff --git a/src/platform/meteorlake/include/platform/lib/shim.h b/src/platform/meteorlake/include/platform/lib/shim.h
@@ -44,11 +44,6 @@
 /** \brief LP RING Oscillator Clock Status */
 #define SHIM_CLKSTS_LROSCCS		BIT(29)
 
-#define L2HSBPM(x)			(0x17A800 + 0x0008 * (x))
-#define SHIM_HSPGCTL(x)			(L2HSBPM(x) + 0x0000)
-
-#define LSPGCTL				0x71D80
-
 #endif /* __PLATFORM_LIB_SHIM_H__ */
 
 #else

diff --git a/src/platform/tigerlake/include/platform/lib/shim.h b/src/platform/tigerlake/include/platform/lib/shim.h
@@ -224,25 +224,6 @@
 #define I2SLCTL_SPA(x)		BIT(0 + x)
 #define I2SLCTL_CPA(x)		BIT(8 + x)
 
-#define L2LMCAP			0x71D00
-#define L2MPAT			0x71D04
-
-#define HSPGCTL0		0x71D10
-#define HSRMCTL0		0x71D14
-#define HSPGISTS0		0x71D18
-
-#define SHIM_HSPGCTL(x)		(HSPGCTL0 + 0x10 * (x))
-#define SHIM_HSRMCTL(x)		(HSRMCTL0 + 0x10 * (x))
-#define SHIM_HSPGISTS(x)	(HSPGISTS0 + 0x10 * (x))
-
-#define HSPGCTL1		0x71D20
-#define HSRMCTL1		0x71D24
-#define HSPGISTS1		0x71D28
-
-#define LSPGCTL			0x71D50
-#define LSRMCTL			0x71D54
-#define LSPGISTS		0x71D58
-
 #define SHIM_L2_MECS		(SHIM_BASE + 0xd0)
 
 /** \brief LDO Control */

diff --git a/west.yml b/west.yml
@@ -43,7 +43,7 @@ manifest:
 
     - name: zephyr
       repo-path: zephyr
-      revision: 2ccf775396c225f4398db1014886397a91f6d42f
+      revision: pull/70221/head
       remote: zephyrproject
 
       # Import some projects listed in zephyr/west.yml@revision