SAI: fix DSP_A/B frame sync pulse

SAI can be configured for a one bclk wide frame sync pulse
by setting CR4 SYWD to 0. The REG_SAI_CR4_SYWD()
macro subtracts 1 from its argument which resulted in
bad things happening. So use 1 as correct macro argument.

Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>

src/drivers/imx/sai.c

@@ -284,15 +284,15 @@ static inline int sai_set_config(struct dai *dai, struct ipc_config_dai *common_
 		 */
 		val_cr2 |= REG_SAI_CR2_BCP;
 		val_cr4 |= REG_SAI_CR4_FSE;
-		val_cr4 |= REG_SAI_CR4_SYWD(0U);
+		val_cr4 |= REG_SAI_CR4_SYWD(1U);
 		break;
 	case SOF_DAI_FMT_DSP_B:
 		/*
 		 * Frame high, one bit for frame sync,
 		 * frame sync asserts with the first bit of the frame.
 		 */
 		val_cr2 |= REG_SAI_CR2_BCP;
-		val_cr4 |= REG_SAI_CR4_SYWD(0U);
+		val_cr4 |= REG_SAI_CR4_SYWD(1U);
 		break;
 	case SOF_DAI_FMT_PDM:
 		val_cr2 |= REG_SAI_CR2_BCP;