ipc: add cache flushing and invalidation for IPC data

This patch addresses an issue with incorrect IPC responses due to the
lack of cache flushing and invalidation on secondary cores.

The following changes have been made:

1. Added cache writeback for IPC message data in `ipc_msg_send` when the
   current core is not the primary core.
2. Added cache invalidation for IPC message data in
   `ipc_prepare_to_send` before writing to the mailbox.

These changes ensure that the IPC data is correctly synchronized between
cores.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>

src/ipc/ipc-common.c

@@ -214,6 +214,9 @@ void ipc_msg_send(struct ipc_msg *msg, void *data, bool high_priority)
 	    msg->tx_data != data) {
 		ret = memcpy_s(msg->tx_data, msg->tx_size, data, msg->tx_size);
 		assert(!ret);
+		if (!cpu_is_primary(cpu_get_id()))
+			dcache_writeback_region((__sparse_force void __sparse_cache *)msg->tx_data,
+						msg->tx_size);
 	}
 
 	/*

src/ipc/ipc4/handler.c

@@ -1494,8 +1494,11 @@ struct ipc_cmd_hdr *ipc_prepare_to_send(const struct ipc_msg *msg)
 	msg_data.msg_out.pri = msg->header;
 	msg_data.msg_out.ext = msg->extension;
 
-	if (msg->tx_size)
+	if (msg->tx_size) {
+		dcache_invalidate_region((__sparse_force void __sparse_cache *)msg->tx_data,
+					 msg->tx_size);
 		mailbox_dspbox_write(0, (uint32_t *)msg->tx_data, msg->tx_size);
+	}
 
 	/* free memory for get config function */
 	if (msg == &msg_reply && msg_reply.tx_size > 0) {