schedule: zephyr_dma_domain: Add support for shared IRQs

In the case of DMA channels using the same IRQ line
the same interrupt handler with different data is
registered multiple times for the same interrupt.

This approach works perfectly fine when using the IRQ_STEER
IP since the way its driver works is it allows registering
multiple handlers+data for the same INTID.

When switching to ARM64, this approach no longer works since
the last irq_handler/irq_data pair will overwrite the previous
one for the same INTID. Because of this, the IRQ bit from the
DMA channel may not get cleared when multiple pipeline tasks
are scheduled. This reasoning applies to the ARM64 architecture
with GICv3 interrupt controller.

To overcome this, the Zephyr DMA domain now holds a list
of channels using the same IRQ. When the DMA IRQ gets triggered,
the handler will iterate through the list of channels using the
same IRQ and clear the interrupt.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>