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Add mt8195 platform specific changes #4725

Merged
merged 3 commits into from
Sep 10, 2021
Merged

Add mt8195 platform specific changes #4725

merged 3 commits into from
Sep 10, 2021

Commits on Sep 10, 2021

  1. xtensa: exception: Add XCHAL_INTLEVEL5_MASK 

    This results in a compiler error
when xtensa configuration has no IRQ level 5.
Make it use core-isa.h.

Error:
invalid register 'EPC5' for 'rsr' instruction
Error:
invalid register 'EPS5' for 'rsr' instruction

For mt8195, we don't support those instrucations

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
    @kuanhsuncheng
    kuanhsuncheng authored and Allen-kh Cheng committed Sep 10, 2021
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  2. xtensa: add mt8195 MPU setup 

    Override the default MPU setup.
This table matches the mt8195 memory map

Add xtensa/mpuasm.h, for mpu_write_map opcode

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
    @kuanhsuncheng
    kuanhsuncheng authored and Allen-kh Cheng committed Sep 10, 2021
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  3. xtensa: add atomic and spinlock function with exclusive 

    In mp_asm.S, if XCHAL_HAVE_EXCLUSIVE is defined,
it will use exclusive instructions,
else it will use s32c1i instructions.

It supports S32C1I and exclusive instruction in xthal_compare_and_set() API.
Refer to xtos-simc-mutex.c, xtos_mutex_p structure is similar to spinlock_t.

For dsp design, we cannot use s32c1i intrcutions in mt8195.

In order to not affect other platform, add CONFIG_XTENSA_EXCLUSIVE and __XCC__
compile options.

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
    Allen-kh Cheng committed Sep 10, 2021
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