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Enabling probe feature in AMD Platforms #8634

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merged 7 commits into from
Jan 3, 2024
Merged

Enabling probe feature in AMD Platforms #8634

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a1b8cbc
probe: small fixes in probe functionality.
DINESHKUMARK1 Dec 14, 2023
00411bd
dma-copy: remove CONFIG_DMA_GW macro.
DINESHKUMARK1 Dec 13, 2023
82792c1
amd: add ACP_FUTURE_REG_ACLK_0 Register in AMD/Renoir Platform.
DINESHKUMARK1 Dec 18, 2023
1829eef
amd: add ACP_FUTURE_REG_ACLK_0 Register in AMD/Acp_6_3 Platform.
DINESHKUMARK1 Dec 18, 2023
60acfae
amd: add probe functionality in AMD/rembrandt platform.
DINESHKUMARK1 Dec 20, 2023
0211ca5
amd: add probe functionality in AMD/vangogh platform.
DINESHKUMARK1 Dec 20, 2023
58bd139
amd: add probe functionality in AMD platforms.
DINESHKUMARK1 Dec 20, 2023
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2 changes: 2 additions & 0 deletions src/arch/xtensa/configs/rembrandt_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -33,3 +33,5 @@ CONFIG_COMP_TDFB=n
##CONFIG_COMP_MUX=n
CONFIG_COMP_SEL=n
CONFIG_COMP_MIXER=n
CONFIG_PROBE=y
CONFIG_PROBE_POINTS_MAX=16
2 changes: 2 additions & 0 deletions src/arch/xtensa/configs/vangogh_defconfig
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Expand Up @@ -24,3 +24,5 @@ CONFIG_COMP_ASRC=n
CONFIG_TRACE=y
CONFIG_TRACEE=y
CONFIG_TRACEV=y
CONFIG_PROBE=y
CONFIG_PROBE_POINTS_MAX=16
50 changes: 37 additions & 13 deletions src/drivers/amd/common/acp_dma.c
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Expand Up @@ -22,10 +22,15 @@
#include <stddef.h>
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Can you please add more details about what 'probe' functionality is?

Is the ability to get some statistics/logs via compress interface?

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@DINESHKUMARK1 DINESHKUMARK1 Dec 19, 2023 •
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Hi,
This is a debug feature to probe the data in between components of pipeline, for more information find the below link

https://thesofproject.github.io/latest/developer_guides/debugability/probes/index.html

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@dbaluta its already used on Intel platforms. Kernel parts also upstream.

#include <stdint.h>
#include <platform/acp_dma.h>
#include <sof/probe/probe.h>

DECLARE_SOF_UUID("acpdma", acpdma_uuid, 0x70f2d3f2, 0xcbb6, 0x4984,
0xa2, 0xd8, 0x0d, 0xd5, 0x14, 0xb8, 0x0b, 0xc2);
DECLARE_TR_CTX(acpdma_tr, SOF_UUID(acpdma_uuid), LOG_LEVEL_INFO);
#define PROBE_UPDATE_POS_MASK 0x80000000
#define PROBE_BUFFER_WATERMARK (16 * 1024)
static uint32_t probe_pos_update, probe_pos;


void dma_config_descriptor(uint32_t dscr_start_idx, uint32_t dscr_count,
acp_cfg_dma_descriptor_t *psrc_dscr,
Expand Down Expand Up @@ -73,6 +78,17 @@ static struct dma_chan_data *acp_dma_channel_get(struct dma *dma,
acp_dma_chan->config[req_chan].rd_size = 0;
acp_dma_chan->config[req_chan].wr_size = 0;
acp_dma_chan->config[req_chan].size = 0;
acp_dma_chan->config[req_chan].probe_channel = 0xFF;
if (dma->priv_data) {
acp_dma_chan->config[req_chan].probe_channel = *(uint32_t *)dma->priv_data;
if (acp_dma_chan->config[req_chan].probe_channel == channel->index) {
/*probe update pos & flag*/
probe_pos_update = 0;
probe_pos = 0;
io_reg_write(PU_REGISTER_BASE + ACP_FUTURE_REG_ACLK_0,
PROBE_UPDATE_POS_MASK);
}
}
return channel;
}

Expand All @@ -88,6 +104,15 @@ static void acp_dma_channel_put(struct dma_chan_data *channel)
/* reset read and write pointer */
acp_dma_chan->config[channel->index].rd_size = 0;
acp_dma_chan->config[channel->index].wr_size = 0;
acp_dma_chan->config[channel->index].size = 0;
if (acp_dma_chan->config[channel->index].probe_channel == channel->index) {
acp_dma_chan->config[channel->index].probe_channel = 0XFF;
probe_pos_update = 0;
probe_pos = 0;
/*probe update pos & flag*/
io_reg_write(PU_REGISTER_BASE + ACP_FUTURE_REG_ACLK_0,
PROBE_UPDATE_POS_MASK);
}
}

/* Stop the requested channel */
Expand Down Expand Up @@ -205,9 +230,10 @@ static int acp_dma_copy(struct dma_chan_data *channel, int bytes, uint32_t flags
.elem.size = bytes,
};
acp_dma_ch_sts_t ch_sts;
struct acp_dma_chan_data *acp_dma_chan;
uint32_t dmach_mask = (1 << channel->index);
int ret = 0;

acp_dma_chan = dma_chan_get_data(channel);
if (channel->index != DMA_TRACE_CHANNEL)
amd_dma_reconfig(channel, bytes);

Expand All @@ -218,7 +244,16 @@ static int acp_dma_copy(struct dma_chan_data *channel, int bytes, uint32_t flags
while (ch_sts.bits.dmachrunsts & dmach_mask)
ch_sts = (acp_dma_ch_sts_t)dma_reg_read(channel->dma, ACP_DMA_CH_STS);
ret = acp_dma_stop(channel);

if (ret >= 0 && acp_dma_chan->config[channel->index].probe_channel == channel->index) {
probe_pos_update += bytes;
probe_pos += bytes;
if (probe_pos >= PROBE_BUFFER_WATERMARK) {
io_reg_write(PU_REGISTER_BASE + ACP_FUTURE_REG_ACLK_0,
PROBE_UPDATE_POS_MASK | probe_pos_update);
acp_dsp_to_host_intr_trig();
probe_pos = 0;
}
}
notifier_event(channel, NOTIFIER_ID_DMA_COPY,
NOTIFIER_TARGET_CORE_LOCAL, &next, sizeof(next));
return ret;
Expand All @@ -241,17 +276,6 @@ static int acp_dma_set_config(struct dma_chan_data *channel,

channel->direction = config->direction;
dir = config->direction;
if (config->cyclic) {
tr_err(&acpdma_tr,
"DMA: cyclic configurations are not supported");
return -EINVAL;
}
if (config->scatter) {
tr_err(&acpdma_tr,
"DMA: scatter is not supported Chan.Index %d scatter %d",
channel->index, config->scatter);
return -EINVAL;
}
return dma_setup(channel, &config->elem_array, dir);
}

Expand Down
5 changes: 4 additions & 1 deletion src/drivers/amd/rembrandt/acp_dma.c
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Expand Up @@ -238,8 +238,11 @@ int dma_setup(struct dma_chan_data *channel,
(dma_config_dscr[dscr_strt_idx].src_addr &
ACP_DRAM_ADDRESS_MASK);
dma_cfg->base = dma_config_dscr[dscr_strt_idx].src_addr | ACP_SRAM;
dma_cfg->wr_size = dma_cfg->size;
dma_cfg->rd_size = 0;
if (channel->index == dma_cfg->probe_channel)
dma_cfg->wr_size = 0;
else
dma_cfg->wr_size = dma_cfg->size;
}
}
}
Expand Down
5 changes: 4 additions & 1 deletion src/drivers/amd/vangogh/acp_dma.c
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Expand Up @@ -242,8 +242,11 @@ int dma_setup(struct dma_chan_data *channel,
dma_cfg->base =
dma_config_dscr[dscr_strt_idx].src_addr |
ACP_DRAM_ADDR_TRNS;
dma_cfg->wr_size = dma_cfg->size;
dma_cfg->rd_size = 0;
if (channel->index == dma_cfg->probe_channel)
dma_cfg->wr_size = 0;
else
dma_cfg->wr_size = dma_cfg->size;
}
}
}
Expand Down
3 changes: 0 additions & 3 deletions src/ipc/dma-copy.c
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Expand Up @@ -184,8 +184,6 @@ int dma_copy_new(struct dma_copy *dc)
return 0;
}

#if CONFIG_DMA_GW

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this config is not AMD specific, if AMD platform want to use this, better to add this config to AMD build?

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Enabling CONFIG_DMA_GW will bring in many other API's which will cause failures in DMA operations and are not required on AMD platform, but dma_copy_set_stream_tag is required for enabling DMA channel based on stream tag, That is the reason to remove CONFIG_DMA_GW for this API, I believe this won't affect non AMD platforms.

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yeah, this is fine - its mostly generic if anyone is using a DMA tag to identify a DMA channel.

int dma_copy_set_stream_tag(struct dma_copy *dc, uint32_t stream_tag)
{
/* get DMA channel from DMAC */
Expand All @@ -198,4 +196,3 @@ int dma_copy_set_stream_tag(struct dma_copy *dc, uint32_t stream_tag)
return 0;
}

#endif
1 change: 1 addition & 0 deletions src/platform/amd/acp_6_3/include/platform/chip_offset_byte.h
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Expand Up @@ -31,6 +31,7 @@
#define ACP_SW_INTR_TRIG 0x1241810
#define DSP_INTERRUPT_ROUTING_CTRL_0 0x1241814
#define DSP_INTERRUPT_ROUTING_CTRL_1 0x1241818
#define ACP_FUTURE_REG_ACLK_0 0x1241854
#define ACP_AXI2DAGB_SEM_0 0x1241874
#define ACP_DSP0_INTR_CNTL1 0x1241920
#define ACP_DSP0_INTR_STAT1 0x1241924
Expand Down
2 changes: 2 additions & 0 deletions src/platform/amd/common/include/platform/acp_dma.h
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Expand Up @@ -32,6 +32,8 @@ struct acp_dma_config {
uint32_t sys_buff_size;
/* virtual system memory offset for system memory buffer */
uint32_t phy_off;
/* probe_channel id */
uint32_t probe_channel;
};

struct acp_dma_chan_data {
Expand Down
1 change: 1 addition & 0 deletions src/platform/amd/rembrandt/include/platform/chip_offset_byte.h
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Expand Up @@ -34,6 +34,7 @@
#define ACP_SW_INTR_TRIG 0x1241810
#define DSP_INTERRUPT_ROUTING_CTRL_0 0x1241814
#define DSP_INTERRUPT_ROUTING_CTRL_1 0x1241818
#define ACP_FUTURE_REG_ACLK_0 0x1241854
#define ACP_AXI2DAGB_SEM_0 0x1241874
#define ACP_DSP0_INTR_CNTL1 0x1241920
#define ACP_DSP0_INTR_STAT1 0x1241924
Expand Down
1 change: 1 addition & 0 deletions src/platform/amd/renoir/include/platform/chip_offset_byte.h
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Expand Up @@ -32,6 +32,7 @@
#define ACP_SW_INTR_TRIG 0x124181C
#define ACP_SMU_MAILBOX 0x1241820
#define DSP_INTERRUPT_ROUTING_CTRL 0x1241824
#define ACP_FUTURE_REG_ACLK_0 0x1241860
#define ACP_TIMER 0x1241874
#define ACP_TIMER_CNTL 0x1241878
#define ACP_AXI2DAGB_SEM_0 0x1241880
Expand Down
1 change: 1 addition & 0 deletions src/platform/amd/vangogh/include/platform/chip_offset_byte.h
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Expand Up @@ -33,6 +33,7 @@
#define ACP_SMU_MAILBOX 0x1241820
#define DSP_INTERRUPT_ROUTING_CTRL_0 0x1241824
#define DSP_INTERRUPT_ROUTING_CTRL_1 0x1241828
#define ACP_FUTURE_REG_ACLK_0 0x1241864

#define ACP_TIMER 0x1241878
#define ACP_TIMER_CNTL 0x124187C
Expand Down
26 changes: 12 additions & 14 deletions src/probe/probe.c
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Expand Up @@ -132,7 +132,6 @@ static int probe_dma_buffer_init(struct probe_dma_buf *buffer, uint32_t size,
*/
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static int probe_dma_init(struct probe_dma_ext *dma, uint32_t direction)
{
struct dma_sg_config config = { 0 };
uint32_t elem_addr, addr_align;
const uint32_t elem_size = sizeof(uint64_t) * DMA_ELEM_SIZE;
const uint32_t elem_num = PROBE_BUFFER_LOCAL_SIZE / elem_size;
Expand All @@ -151,7 +150,7 @@ static int probe_dma_init(struct probe_dma_ext *dma, uint32_t direction)
tr_err(&pr_tr, "probe_dma_init(): dma->dc.dmac = NULL");
return -ENODEV;
}

dma->dc.dmac->priv_data = &dma->dc.dmac->chan->index;
/* get required address alignment for dma buffer */
#if CONFIG_ZEPHYR_NATIVE_DRIVERS
err = dma_get_attribute(dma->dc.dmac->z_dev, DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT,
Expand All @@ -174,22 +173,19 @@ static int probe_dma_init(struct probe_dma_ext *dma, uint32_t direction)

elem_addr = (uint32_t)dma->dmapb.addr;

config.direction = direction;
config.src_width = sizeof(uint32_t);
config.dest_width = sizeof(uint32_t);
config.cyclic = 0;
dma->config.direction = direction;
dma->config.src_width = sizeof(uint32_t);
dma->config.dest_width = sizeof(uint32_t);
dma->config.cyclic = 0;

err = dma_sg_alloc(&config.elem_array, SOF_MEM_ZONE_RUNTIME,
config.direction, elem_num, elem_size, elem_addr, 0);
err = dma_sg_alloc(&dma->config.elem_array, SOF_MEM_ZONE_RUNTIME,
dma->config.direction, elem_num, elem_size, elem_addr, 0);
if (err < 0)
return err;

err = dma_set_config_legacy(dma->dc.chan, &config);
err = dma_set_config_legacy(dma->dc.chan, &dma->config);
if (err < 0)
return err;

dma_sg_free(&config.elem_array);

return 0;
}
#else
Expand Down Expand Up @@ -261,6 +257,7 @@ static int probe_dma_init(struct probe_dma_ext *dma, uint32_t direction)
static int probe_dma_deinit(struct probe_dma_ext *dma)
{
int err = 0;
dma_sg_free(&dma->config.elem_array);
#if CONFIG_ZEPHYR_NATIVE_DRIVERS
err = dma_stop(dma->dc.dmac->z_dev, dma->dc.chan->index);
#else
Expand Down Expand Up @@ -1421,9 +1418,10 @@ int probe_point_remove(uint32_t count, const uint32_t *buffer_id)
#else
dev = ipc_get_comp_by_id(ipc_get(), buffer_id[i]);
if (dev) {
notifier_unregister(_probe, dev->cb,
notifier_unregister(&buf_id->full_id, dev->cb,
NOTIFIER_ID_BUFFER_PRODUCE);
notifier_unregister(_probe, dev->cb, NOTIFIER_ID_BUFFER_FREE);
notifier_unregister(&buf_id->full_id, dev->cb,
NOTIFIER_ID_BUFFER_FREE);
}
#endif
_probe->probe_points[j].stream_tag =
Expand Down