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tools: topology1: imx8ulp: correct BCLK rate and change BCLK polarity and protocol #8978

Merged
merged 3 commits into from
Mar 25, 2024
Merged

tools: topology1: imx8ulp: correct BCLK rate and change BCLK polarity and protocol #8978

merged 3 commits into from
Mar 25, 2024

Commits on Mar 22, 2024

  1. tools: topology1: imx8ulp: rename RATE to FSYNC_RATE 

    Rename the `RATE` parameter to `FSYNC_RATE` in order to
remove ambiguity regarding what the parameter is.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
    @LaurentiuM1234
    LaurentiuM1234 committed Mar 22, 2024
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  2. tools: topology1: imx8ulp: correct BCLK frequency 

    8ULP has two supported BT HFP scenarios: NBS and WBS. For
NBS the frequency of FSYNC is 8k, while for WBS the frequency
of FSYNC is 16k. Since the BCLK is computed as:
	Freq(BCLK) = TDM_SLOTS * TDM_SLOT_WIDTH * Freq(FSYNC)
then that means we're going to end up with two different BCLK
frequencies (one for each supported scenario).

Currently, what we do is pass the frequency of FSYNC
as a build argument, while keeping the frequency of BCLK
constant (set to 256000, which would be the same value as the
one used in WBS). This causes the following issues:

	1) The Zephyr native SAI driver returns an error
	when trying to commit the configuration because the
	frequency of BCLK doesn't abide by the aforementioned
	formula.

	2) We end up consuming twice as many samples in a given
	unit of time.

To fix these issues, use the aforementioned formula to compute
the frequency of BCLK.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
    @LaurentiuM1234
    LaurentiuM1234 committed Mar 22, 2024
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  3. tools: topology1: imx8ulp: change protocol and BCLK polarity 

    The BT codec used by the IW416 chip expects FSYNC to be
asserted for only one BCLK. Also, FSYNC should be active HIGH.
As such, change from I2S protocol to DSP_A protocol since the
configurations made for this protocol inside the SAI driver
are more suited.

Also, by default, the BT codec drives data on BCLK rising
edge and samples it on falling edge. With the DSP_A protocol,
the SAI driver also has the same configuration, which is wrong
since we can't drive and sample on the same edge and cycle. As such,
invert BCLK polarity such that the SAI will drive on rising edge
and sample on falling edge.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
    @LaurentiuM1234
    LaurentiuM1234 committed Mar 22, 2024
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