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[MTL-006] soc: intel_adsp: sram: enable retention mode #71

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merged 4 commits into from
Oct 17, 2023
Merged

[MTL-006] soc: intel_adsp: sram: enable retention mode #71

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da97ec8
soc: intel_adsp: hpsram init refactor
tmleman Oct 13, 2023
88cb640
soc: intel_adsp: lpsram init refactor
tmleman Oct 13, 2023
66a6f8f
soc: intel_adsp: hpsram enable retention mode
tmleman Oct 13, 2023
29d4ed8
soc: intel_adsp: lpsram enable retention mode
tmleman Oct 17, 2023
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19 changes: 19 additions & 0 deletions soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -147,6 +147,18 @@ struct ace_hpsram_regs {
uint8_t HSxPGISTS;
uint8_t reserved1[3];
};

struct ace_lpsram_regs {
/** @brief power gating control */
uint8_t USxPGCTL;
/** @brief retention mode control */
uint8_t USxRMCTL;
uint8_t reserved[2];
/** @brief power gating status */
uint8_t USxPGISTS;
uint8_t reserved1[3];
};

#endif

/* These registers are for the L2 HP SRAM bank power management control and status.*/
Expand All @@ -156,4 +168,11 @@ struct ace_hpsram_regs {
#define HPSRAM_REGS(block_idx) ((volatile struct ace_hpsram_regs *const) \
(L2HSBPM_REG + L2HSBPM_REG_SIZE * (block_idx)))

/* These registers are for the L2 LP SRAM bank power management control and status.*/
#define L2LSBPM_REG 0x71D80
#define L2LSBPM_REG_SIZE 0x0008

#define LPSRAM_REGS(block_idx) ((volatile struct ace_lpsram_regs *const) \
(L2LSBPM_REG + L2LSBPM_REG_SIZE * (block_idx)))

#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_ */
14 changes: 6 additions & 8 deletions soc/xtensa/intel_adsp/ace/sram.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,15 +20,14 @@ __imr void hp_sram_init(uint32_t memory_size)
ARG_UNUSED(memory_size);

uint32_t hpsram_ebb_quantity = ace_hpsram_get_bank_count();
volatile uint32_t *l2hsbpmptr = (volatile uint32_t *)ACE_L2MM->l2hsbpmptr;
volatile uint8_t *status = (volatile uint8_t *)l2hsbpmptr + 4;
uint32_t idx;

for (idx = 0; idx < hpsram_ebb_quantity; ++idx) {
*(l2hsbpmptr + idx * 2) = 0;
HPSRAM_REGS(idx)->HSxPGCTL = 0;
HPSRAM_REGS(idx)->HSxRMCTL = 1;
}
for (idx = 0; idx < hpsram_ebb_quantity; ++idx) {
while (*(status + idx * 8) != 0) {
while (HPSRAM_REGS(idx)->HSxPGISTS != 0) {
}
}

Expand All @@ -38,15 +37,14 @@ __imr void hp_sram_init(uint32_t memory_size)
__imr void lp_sram_init(void)
{
uint32_t lpsram_ebb_quantity = ace_lpsram_get_bank_count();
volatile uint32_t *l2usbpmptr = (volatile uint32_t *)ACE_L2MM->l2usbpmptr;
volatile uint8_t *status = (volatile uint8_t *)l2usbpmptr + 4;
uint32_t idx;

for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
*(l2usbpmptr + idx * 2) = 0;
LPSRAM_REGS(idx)->USxPGCTL = 0;
LPSRAM_REGS(idx)->USxRMCTL = 1;
}
for (idx = 0; idx < lpsram_ebb_quantity; ++idx) {
while (*(status + idx * 8) != 0) {
while (LPSRAM_REGS(idx)->USxPGISTS != 0) {
}
}

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