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clock-tree-synthesis

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KAMATHAM19 / RTL-to-GDSII-ASIC-design-of-Counter

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The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

simulation routing rtl synthesis placement sta gdsii floorplan coverage-analysis powerplan physical-verification clock-tree-synthesis rc-extraction
  • Updated Jul 13, 2024
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