Haskell to VHDL/Verilog/SystemVerilog compiler
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Updated
Jan 3, 2025 - Haskell
Haskell to VHDL/Verilog/SystemVerilog compiler
Hardware Description Languages
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
SystemRDL 2.0 language compiler front-end
Fearless hardware design
A core language for rule-based hardware design 🦑
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
Control and status register code generator toolchain
ACT hardware description language and core tools.
Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…
A new Hardware Design Language that keeps you in the driver's seat
VHDL Guide
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
A place to keep my synthesizable verilog examples.
🔁 elastic circuit toolchain
📚Repositório da Disciplina INE5406 - Sistemas Digitais
design and verification of asynchronous circuits
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