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iverilog

Here are 76 public repositories matching this topic...

mshr-h / vscode-verilog-hdl-support

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Dec 18, 2024
TypeScript

TimRudy / ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

fpga open-hardware eda digital-logic icestorm iverilog logic-circuit verilog-components 7400

Updated Nov 20, 2024
Verilog

ashishrana160796 / verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

practice embedded-systems verilog up-for-grabs circuit switches beginner-friendly logic-gates hdl verilog-hdl iverilog verilog-snippets verilog-programs verilog-project

Updated Nov 25, 2020
Verilog

TheSUPERCD / 8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Nov 30, 2022
Verilog

sgherbst / svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

JeffDeCola / my-verilog-examples

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Jul 10, 2023
Verilog

TimRudy / uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

fpga open-hardware eda digital-logic hardware-designs serialport icestorm uart-verilog iverilog verilog-components uart-interface

Updated May 28, 2023
Verilog

Essenceia / ethernet-physical-layer

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

c fpga rtl verilog ethernet iverilog vpi pcs 10gbase-r 40gbase-r

Updated Jan 2, 2024
Tcl

maazm007 / vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

gcc-complier gtkwave verilog-hdl yosys risc-v iverilog objdump vlsi-design

Updated May 12, 2024
C

yasnakateb / PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

pangguoming / iview-admin

Vue 2.0 admin management system template based on iView 个人修改版

vue admin-dashboard iverilog

Updated Mar 1, 2018
JavaScript

jfcherng-sublime / SublimeLinter-contrib-iverilog

This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).

sublime-text sublimelinter linter-plugin verilog iverilog

Updated Apr 16, 2024
Python

patrickleboutillier / jcscpu-hw

Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

fpga verilog vivado iverilog

Updated Aug 3, 2020
Verilog

u3oR / fft_verilog

使用verilog实现流水线 FFT

pipeline verilog fft iverilog

Updated Jul 1, 2024
Verilog

KiranThomasCherian / VLSI-and-Computer-Architecture

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

pipeline verilog xilinx floating-point computer-architecture vlsi hardware-modules adder wallace-tree-multiplier iverilog floating-point-arithmetic pipelined carry-propogate-adders kogge-stone-adder sklansky-adder magic-tool gate-layout cmos-path-enumerator

Updated May 8, 2021
Verilog

pytec8800 / pint_iverilog

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

simulation rtl risc-v iverilog

Updated Nov 15, 2021
C++

rodrigomelo9 / verifying-foss-hdl-synthesizers

a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated Sep 26, 2020
Makefile

dpretet / meduram

Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface

Updated Apr 21, 2021
SystemVerilog

OpenEDF / verilog-basic

learn the combinational and sequential logic circuit.

simulator fpga simulation vhdl verilog iverilog ice40up5k fpga-programming synopsys-vcs synopsys-dc

Updated Oct 5, 2024
SystemVerilog

yasnakateb / NoCRouter

👶🏻 My first baby steps into the world of NoC

router verilog icarus-verilog verilog-hdl iverilog

Updated Sep 1, 2022
Verilog

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