A simple MOSFET model with only 5-DC-parameters for circuit simulation
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Jun 25, 2024
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icdesign
Here are 6 public repositories matching this topic...
Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
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Jul 30, 2024 - Verilog
Design of Differential Input Single Ended Output Single Stage Amplifier
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Sep 15, 2021
Inter-OS Migration of CAD Tools for IC Design
java open-source opensource magic perl foss tcl eda cad design-flow tcl-tk icdesign interos-migration
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Jun 5, 2023
The SPI Slave with Single Port RAM project demonstrates the implementation of a high-performance SPI slave interface with integrated single-port RAM. The design utilizes a finite state machine (FSM) with different encoding styles to achieve optimal timing performance.
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Jan 4, 2025 - Verilog
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