Verilog Implementation of an ARM LEGv8 CPU

Graphical-Micro-Architecture-Simulator

LEGv8 CPU implementation and some tools like a LEGv8 assembler

A LEGv8 Assembly editor and emulator.

Graphical-Micro-Architecture-Simulator

Simulator for LEG-V8 Assembly in Rust, as well as other tools for facilitating LEG-V8 development.

A LEGv8 Assembly extension for Visual Studio Code.

ARM Assembly Gradient Descent Program

A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog

Simplified, monocycle version of the LEGv8 processor designed by PCS Poli-USP and implemented in VHDL for Digital Systems II

Verilog Implementation of an ARM LEGv8 CPU

Home for my Verilog labs

C++ disassembler for the LEGv8 subset of ARM.

Engineered low-level microcontroller programs for real-time GPIO control, data processing, and registerlevel manipulation. Assembled and configured hardware setups, including microcontroller boards and interfacing GPIO pins with LEDs and buttons

A disassembler for LEGv8 machine code as required by Computer Science 321 @ Iowa State University, Fall 2021.

Parser for legv8sim from Nom that converts to an intermediate representation to interpret a legv8 program

Code for COEN122: Computer Architecture

Bitonic Sort in a simplified ARMv8 Assembly language

A LEGv8 Language Server that implements the Microsof Language Server Protocol.

Insertion sort implemented in LEGv8 assembly as required by Computer Science 321 @ Iowa State University, Fall 2021.