Teaching Materials for Dr. Waleed A. Yousef

Automatically interpret and validate nested natural logic arguments based on rules of inference and propositional logic

All the homeworks, studies and projects I've done at Metu-CENG

Water Level Meter

EventNext is logic interface design actors components for .net core

Circuit Builder Desktop Application (like mmlogic) made with Electron + React Typescript. Compatible with Windows, Mac and Linux.

Logic Minimization in Python

All the homeworks, testers and projects done at METU-CENG

SystemVerilog examples for a digital design course

ELVE : ELVE Logic Visualization Engine

Projects of a CSE student at Marmara University

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

All the homeworks, testers and projects done at Marmara University, Computer Science & Engineering

A collection of digital logic circuits

Automated conversion from CHP to PRS using syntax-directed translation

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

Homeworks given at Department of Computer Engineering, Middle East Technical University.

Educational Project for Logic Design 1 course taken during Fall 2021 semester.

A puzzle game for iOS.

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.