CPLD gateware for the Sinara Mirny module.

Migen framework examples

Hardware Motion and Motor Control Library

A Python toolbox for building complex digital hardware [fork for adding nexsys3 support]

A simple C++ project configured for use with Visual Studio Code, including IntelliSense support, custom file associations, and a GitHub Actions workflow for continuous integration. COA LiTEX

A unit-test framework for testing Migen modules directely on hardware.

WARC Open Fusesoc Cores Repository

CPLD gateware for the Sinara Urukul module

Gateware and software for Fastino (32 channel 2.5 MS/s 16 bit DAC for the Sinara ecosystem)

Scripts and gateware for the TinyFPGA bx

Describing RTL circuit in Ruby

USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface

gateware for the main fpga, including a hispi decoder and image processing

Template project for LiteX-based SoCs

Open source Logic Analyzer based on LiteX SoC

AXI support for Migen/MiSoC

FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.

Support files for participating in a Fomu workshop