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zynq-7000

Here are 95 public repositories matching this topic...

xddcore / OpenNNA

一个开源的FPGA神经网络加速器。

fpga hls tensorflow zynq-7000

Updated Sep 4, 2023
C++

hz12opensource / libresdr

Firmware with overclock support for LibreSDR (PlutoSDR clone with Zynq 7020), 27.5 MSPS sample rate over Gigabit Ethernet with libiio/PlutoSDR API

zynq overclock zynq-7000 plutosdr overclocking plutosdr-fw plutosdr-firmware zynq-7020 libresdr antsdr plutoplus libresdr-fw

Updated Jan 21, 2024
Shell

Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP

Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP

java i2c freertos adc lwip ethernet tcp-ip fpga-soc dma zynq-7000 z-turn ad9288 ad9577

Updated Jun 23, 2021
VHDL

beehive-lab / FastPath_MP

FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD

fpga nvme zynq-7000

Updated Apr 20, 2021
C

MakarenaLabs / Common-PL-Devices-on-PYNQ

Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)

fpga xilinx pynq zynq-7000

Updated Jul 7, 2021
Jupyter Notebook

NekoSilverFox / ZYNQ

⚙️ 基于 Zynq-7 全可编程 SoC 的设计

sdk fpga zynq verilog xilinx vivado zynq-7010 zynq-7000 soc-fpga zynq-7020 soc-design

Updated Dec 31, 2021
HTML

Hello-FPGA / ZYNQ7020_Core_Board

This is xc7z020clg400 FPGA hardware core board design

fpga hardware fpga-board zynq-7000

Updated Nov 8, 2023

peteut / migen-axi

AXI support for Migen/MiSoC

hdl misoc migen zynq-7000

Updated Jul 21, 2024
Python

Teddy-van-Jerry / sdr-psk-fpga

Dual-Mode PSK Transceiver on SDR With FPGA

synchronization fpga zynq amd verilog xilinx sdr vivado transceiver software-defined-radio psk demodulation modulation qpsk bpsk zynq-7000 costas-loop zynq-7020 gardner

Updated Oct 9, 2024
Verilog

zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mm

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

tutorial zynq hls ddr matrix-multiplication vivado zynq-7000

Updated Sep 3, 2019
VHDL

splAcharya / DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

embedded-systems fpga-soc zedboard verilog-hdl xilinx-fpga xilinx-vivado zynq-7000 digital-oscilloscope

Updated Jul 30, 2020

kvm-ip-zynq

ssincan / kvm-ip-zynq

KVM over IP Gateway targeting Zynq-7000 SoC

fpga zynq vhdl xilinx zybo zynq-7000 zybo-z7

Updated Mar 5, 2022
VHDL

b1f6c1c4 / Deep-DarkFantasy

Global Dark Mode for ALL apps on ANY platforms.

fpga zynq dark-theme verilog xilinx vivado verilog-hdl dark-mode zynq-7000 dark-mode-toggle

Updated Oct 3, 2023
Verilog

Stanlazy / ZYNQ_Ruler

Yet Another XC7Z010 Board

zynq pcb pcb-layout zynq-7010 zynq-7000

Updated Mar 22, 2022

Stanlazy / 7z010_ddr

4-Layer XC7Z010 DDR3 Layout

zynq zynq-7010 zynq-7000 ddr3

Updated Nov 25, 2021

narendiran1996 / vga_controller

Implementation of a VGA Controller in Verilog (Both Graphics Mode and Text Mode)

python fpga verilog vga zybo vga-driver textmode zynq-7000 graphicsmode vga-conroller

Updated Jul 30, 2021
Jupyter Notebook

kimushu / tinythreads

POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000

zynq posix pic32 mips32 nios2 zynq-7000

Updated Jun 14, 2020
C

bselimoglu / SoC-ZedBoard-Zynq-7000-Labs

Hardware and Software Co-design implementations

sdk gpio fsm ddr zedboard dma bram axi zynq-7000 vivado-ip-integrator arm-cortex-a9 zynq7-ps high-performance-port

Updated Dec 5, 2019

KindaM3h / SpaceVNXBaseBoard

SpaceVNX (VITA 74.4) carrier based on Zynq-7000.

hardware pcb jesd204b zynq-7000 ddr3 time-sensitive-networking mipi-csi

Updated Jan 8, 2023

yohanes-erwin / zynq7000

[Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol

zybo zynq-7000 axi4

Updated Feb 22, 2020
Verilog

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