A Simulative MIPS CPU running on Logisim.

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

Large project about Computer Architecture topic. Read and learn how to use MIPS language.

the tiniest MIPS R4300i assembler and disassembler

This is a website for demonstration of how most of the basic instructions work in MIPS architecture

An Iterative Implementation of the Binary Search Algorithm in Assembly Language for the MIPS Architecture.

A pipeline CPU supporting 12 basic MIPS instructions.

A Command-line program that converts MIPS 32 instructions into machine code.

Simulator for MIPS pipeline

🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。

Computers Architecture university project. MIPS document converter to binary computer language.

Customizable and extendable simple mips assembler

QtSpim programs

Implement arithmetic operations to handle half-precision numbers in MIPS instructions.

Program decodes an input machine code. Currently only supports the R, I, and J type instructions listed.

A simulator for the Tomasulo algorithm. It accepts MIPS instructions and shows step by step how these instructions are executed as well as the content of each component in the Tomasulo architecture

C implementation of a 32-bit assembly instruction encoder for MIPS processors, designed to convert MIPS assembly instructions into their corresponding machine code formats for execution on MIPS-based systems.