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neorv32

Here are 18 public repositories matching this topic...

neorv32

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Updated Dec 22, 2024
VHDL

stnolting / neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

cryptography asic fpga entropy random vhdl chaos rtl rng random-number-generators hdl key-generator trng entropy-source ring-oscillator asic-design neorv32

Updated Nov 20, 2024
VHDL

stnolting / fpga_puf

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

security fpga authentication vhdl fingerprint key-generation puf neorv32

Updated Nov 5, 2022
VHDL

stnolting / riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

linux gcc riscv risc-v prebuilt-binaries rv32i neorv32

Updated Mar 16, 2024
Shell

neorv32-verilog

stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Dec 16, 2024
VHDL

stnolting / neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga vhdl intel verilog xilinx lattice soc ghdl yosys risc-v neorv32

Updated Dec 17, 2024
VHDL

SweetAda

gabriele-galeotti / SweetAda

Ada-language framework

Updated Dec 22, 2024
Ada

stnolting / neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

processor vhdl verification riscv isa ghdl risc-v neorv32 riscof sail-riscv

Updated Dec 16, 2024
Python

stnolting / riscv-debug-dtm

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

vhdl gdb debug risc-v openocd jtag neorv32

Updated Jan 6, 2023
VHDL

stnolting / wb_spi_bridge

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

flash fpga memory vhdl spi wishbone xip neorv32

Updated Nov 29, 2021
VHDL

stnolting / neorv32-freertos

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

embedded freertos rtos risc-v neorv32

Updated Dec 16, 2024

islandcontroller / neorv32load

Cross-platform compatible firmware download tool for use with the NEORV32 bootloader, written in Python

python risc-v neorv32

Updated Sep 18, 2021
Python

emb4fun / neorv32-de0n-xboot

A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.

bootloader xmodem neorv32

Updated Nov 2, 2023
C

NeoKaios / neorv32_shadow_stack

Delivrables and code base from a CentraleSupéléc project

school-project low-level risc-v neorv32

Updated Jun 22, 2022
VHDL

emb4fun / neorv32-de0n-fatfs

NEORV32 and a generic FAT file system called FatFs.

fatfs neorv32

Updated Apr 30, 2023
C

Unike267 / Practices

This repo contains the work developed in the SIEAV Master practices 🎓✏️📚

fpga master ghdl vunit neorv32 sieav

Updated Dec 13, 2024
VHDL

stnolting / neorv32-vunit

Simulating the NEORV32 RISC-V Processor using the VUnit testing framework.

testing simulation verification vunit neorv32

Updated Dec 16, 2024
VHDL

CarlosCraveiro / LeNet-5_Moltenware

A LeNet-5 implementation using C language and FPGA, obtaining more performance (Hardware) together with greater versatility (Software), uniting the two worlds. Hardening the Software and Softening the Hardware, to something in between, like Molten Iron, so a Moltenware implementation.

c fpga lenet-5 nios-ii neorv32

Updated Jun 16, 2024
C

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