Network on Chip Simulator

A Chisel RTL generator for network-on-chip interconnects

Network on Chip Implementation written in SytemVerilog

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

Official read only mirror for

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

HLS for Networks-on-Chip

Development of a Network on Chip Simulation using SystemC.

DevJam 2020: In-game NOC boards

cycle accurate Network-on-Chip Simulator

Network on Chip for MPSoC

Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator

System-on-Chip Interconnection Network - Simulation Environment (front-end)

Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research

External Network Operations Center for EPFL SI ISAS-FSD

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

experiments in the vector field

Python modules/classes for easy analysis of Network on Chips