#

powerplanning

Here is 1 public repository matching this topic...

Siddharth13s / RISC-V_Synthesis_and_Physical_Design

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

routing verilog synthesis cts placement tcl-scripts physical-design floorplanning synopsys-dc synopsys-iccii powerplanning

Updated Jul 31, 2024
Verilog

Improve this page

Add a description, image, and links to the powerplanning topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the powerplanning topic, visit your repo's landing page and select "manage topics."