Intel® Performance Counter Monitor (Intel® PCM)

A graphical processor simulator and assembly editor for the RISC-V ISA

GPGPU microprocessor architecture

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

SST Architectural Simulation Components and Libraries

Lightweight recording and sampling of performance counters for specific code segments directly from your C++ application.

A processor cache simulator for the MIPS architecture

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Super scalar Processor design

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

A collection of my cources, lectures, articles and presentations

A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.

Modular Graphical Simulator for Teaching Microprogramming

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

Senior Design Project at UW-Madison ECE