Reverse engineering of the SONY PlayStation CPU.
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Oct 9, 2023 - C++
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standard-cells
Here are 15 public repositories matching this topic...
7 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 1, 2022 - Verilog
9 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 5, 2022 - Verilog
"High density" digital standard cells for SKY130 provided by SkyWater.
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Feb 22, 2023 - Verilog
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
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Apr 30, 2024 - C++
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Low speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Low power" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
Standard cells for SKY90FD provided by SkyWater.
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Jul 28, 2022
"High speed" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
"High voltage" digital standard cells for SKY130 provided by SkyWater.
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Apr 23, 2021 - Verilog
Python-based electronic design automation (EDA) tool for characterizing digital standard cells designed in SKY130 PDK. The characterization process is based in the Synopsys Liberty User Guides and Reference Manual Suite - Version 2017.06
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Jan 10, 2024 - Python
A 12-track height standard cell library built in SKY130 PDK. The cells were designed using Magic VLSI Layout Tool and characterized using Digital Standard Cell Characterizer (DSCC).
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Dec 7, 2023 - Python
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