Documenting the Xilinx 7-series bit-stream format.

FOSS Flow For FPGA

Test suite designed to check compliance with the SystemVerilog standard.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

FPGA tool performance profiling

FPGA Assembly (FASM) Parser and Generator

Random ideas and interesting ideas for things we hope to eventually do.

Upduino v2 with the ice40 up5k FPGA demos

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Project X-Ray Database: XC7 Series

Sphinx Extension which generates various types of diagrams from Verilog code.

SymbiFlow WIP changes for Yosys Open SYnthesis Suite

SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

Python library for working Standard Delay Format (SDF) Timing Annotation files.

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

Tool for graphically viewing FPGA bitstream files and their connection to FASM features.

Library to convert a FASM file into BELs importable into Vivado.

Repository containing common Makefiles for setting up conda environments.

An abstraction library for interfacing EDA tools

generate C++ reader/writer from XSD schema