🤖 Automated helper to make the SymbiFlow project run smoother.
-
Updated
Jun 20, 2020 - Python
🤖 Automated helper to make the SymbiFlow project run smoother.
generate C++ reader/writer from XSD schema
Material Design Html Theme for Sphinx customized for SymbiFlow and related hardware projects.
An abstraction library for interfacing EDA tools
Kokoro Configuration to run against SymbiFlow/vtr-verilog-to-routing repository.
Tool for automatically testing FPGA designs using a Zynq Series 7 board.
Repository containing common Makefiles for setting up conda environments.
Conda build recipes for the toolchains needed by LiteX / MiSoC firmware
Tool for graphically viewing FPGA bitstream files and their connection to FASM features.
Random ideas and interesting ideas for things we hope to eventually do.
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
Python library for working Standard Delay Format (SDF) Timing Annotation files.
Sphinx Extension which generates various types of diagrams from Verilog code.
Add a description, image, and links to the symbiflow topic page so that developers can more easily learn about it.
To associate your repository with the symbiflow topic, visit your repo's landing page and select "manage topics."