librecores / riscv-sodor Star 65 Code Issues Pull requests educational microarchitectures for risc-v isa scala riscv chisel3 firrtl librecores pynq-z1 arty tilelink Updated Feb 18, 2019 Scala
whutddk / Rift2Core Sponsor Star 32 Code Issues Pull requests Discussions Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC. cpu cache riscv chisel3 tilelink rv64gc Updated Feb 6, 2024 Scala
merledu / TileLink Star 21 Code Issues Pull requests TileLink Uncached Lightweight (TL-UL) implementation on Chisel. protocol tilelink Updated Nov 21, 2020 Scala
chipsalliance / OmnixtendEndpoint Star 14 Code Issues Pull requests Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence. asic fpga bluespec coherence tilelink omnixtend Updated May 20, 2024 Bluespec