Fixed addressing for BusAccess impl of Z80

emulator/core/src/memory.rs

@@ -4,7 +4,7 @@ use std::rc::Rc;
 use std::cell::RefCell;
 use std::fmt::Write;
 use femtos::Instant;
-use emulator_hal::{self, BusAccess, Error as EmuError};
+use emulator_hal::{self, BusAccess, ErrorType};
 
 use crate::error::Error;
 use crate::devices::{Address, Addressable, Transmutable, Device, read_beu16};
@@ -413,7 +413,7 @@ where
     }
 }
 
-impl EmuError for Error {}
+impl ErrorType for Error {}
 
 impl BusAccess<u64> for &mut dyn Addressable {
     type Instant = Instant;

emulator/cpus/m68k/src/debugger.rs

@@ -2,7 +2,7 @@
 
 use core::fmt;
 
-use emulator_hal::{Instant as BusInstant, Error as ErrorType, BusAccess, Inspect, Debug};
+use emulator_hal::{Instant as BusInstant, ErrorType, BusAccess, FromAddress, Inspect, Debug};
 
 use crate::{M68k, M68kError, M68kAddress, M68kCycleExecutor};
 
@@ -26,7 +26,7 @@ pub enum M68kInfo {
     State,
 }
 
-impl<Bus, BusError, Instant, Writer> Inspect<Bus, Writer> for M68k<Instant>
+impl<Bus, BusError, Instant, Writer> Inspect<M68kAddress, Bus, Writer> for M68k<Instant>
 where
     Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
     BusError: ErrorType,

emulator/cpus/m68k/src/decode.rs

@@ -1,7 +1,7 @@
 // Instruction Decoding
 
 use core::marker::PhantomData;
-use emulator_hal::{Instant as BusInstant, Error as BusError, BusAccess, Step};
+use emulator_hal::{Instant as BusInstant, ErrorType, BusAccess, Step};
 
 use crate::{M68kType, M68kError, M68kBusPort, M68kAddress, Exceptions};
 use crate::instructions::{

emulator/cpus/m68k/src/execute.rs

@@ -1,6 +1,6 @@
 // Instruction Execution
 
-use emulator_hal::{Instant as BusInstant, Error, BusAccess, Step};
+use emulator_hal::{Instant as BusInstant, ErrorType, BusAccess, Step, FromAddress};
 
 use crate::{M68k, M68kType, M68kError, M68kState};
 use crate::state::{Status, Flags, Exceptions, InterruptPriority};
@@ -72,13 +72,12 @@ where
     }
 }
 
-impl<Bus, BusError, Instant> Step<Bus> for M68k<Instant>
+impl<Bus, BusError, Instant> Step<M68kAddress, Bus> for M68k<Instant>
 where
     Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
-    BusError: Error,
+    BusError: ErrorType,
     Instant: BusInstant,
 {
-    type Instant = Instant;
     type Error = M68kError<BusError>;
 
     fn is_running(&mut self) -> bool {

emulator/cpus/m68k/src/lib.rs

@@ -18,4 +18,4 @@ pub use crate::memory::{M68kAddress, M68kAddressSpace, M68kBusPort};
 pub use crate::decode::{M68kDecoder, InstructionDecoding};
 pub use crate::execute::{M68kCycle, M68kCycleExecutor};
 pub use crate::timing::M68kInstructionTiming;
-//pub use crate::instructions::{Instruction, Target, Size, Sign, XRegister, BaseRegister, IndexRegister, Direction};
+pub use crate::instructions::*;

emulator/cpus/m68k/src/moa.rs

@@ -1,5 +1,5 @@
 use femtos::{Instant, Duration};
-use emulator_hal::{Error as ErrorType, BusAdapter};
+use emulator_hal::{ErrorType, BusAdapter};
 
 use moa_core::{System, Error, Address, Steppable, Interruptable, Addressable, Debuggable, Transmutable};
 
@@ -11,7 +11,7 @@ impl Steppable for M68k<Instant> {
 
         let mut bus = system.bus.borrow_mut();
         let mut adapter: BusAdapter<u32, u64, &mut dyn Addressable, Error> =
-            BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
+            BusAdapter::new(&mut *bus, |addr| addr as u64);
 
         let mut executor = cycle.begin(self, &mut adapter);
         executor.check_breakpoints()?;
@@ -89,7 +89,7 @@ impl Debuggable for M68k<Instant> {
     fn print_current_step(&mut self, system: &System) -> Result<(), Error> {
         let mut bus = system.bus.borrow_mut();
         let mut adapter: BusAdapter<u32, u64, &mut dyn Addressable, Error> =
-            BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
+            BusAdapter::new(&mut *bus, |addr| addr as u64);
 
         // TODO this is called by the debugger, but should be called some other way
         let mut decoder = M68kDecoder::new(self.info.chip, true, self.state.pc);
@@ -107,7 +107,7 @@ impl Debuggable for M68k<Instant> {
 
         let mut bus = system.bus.borrow_mut();
         let mut adapter: BusAdapter<u32, u64, &mut dyn Addressable, Error> =
-            BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
+            BusAdapter::new(&mut *bus, |addr| addr as u64);
 
         decoder.dump_disassembly(&mut adapter, &mut memory, addr as u32, count as u32);
     }

emulator/cpus/m68k/src/tests.rs

@@ -1,7 +1,7 @@
 #[cfg(test)]
 mod decode_unit_tests {
     use femtos::Instant;
-    use emulator_hal::bus::BusAccess;
+    use emulator_hal::BusAccess;
     use emulator_hal_memory::MemoryBlock;
 
     use crate::M68kType;
@@ -13,7 +13,7 @@ mod decode_unit_tests {
 
     fn run_decode_test<F>(cputype: M68kType, mut test_func: F)
     where
-        F: FnMut(&mut InstructionDecoding<'_, MemoryBlock<u32, Instant>, Instant>),
+        F: FnMut(&mut InstructionDecoding<'_, MemoryBlock<Instant>, Instant>),
     {
         let mut memory = MemoryBlock::from(vec![0; 0x0000100]);
         let mut decoder = M68kDecoder::new(cputype, true, 0);
@@ -316,8 +316,7 @@ mod decode_unit_tests {
 #[cfg(test)]
 mod execute_unit_tests {
     use femtos::{Instant, Frequency};
-    use emulator_hal::bus::BusAccess;
-    use emulator_hal::step::Step;
+    use emulator_hal::{Step, BusAccess};
     use emulator_hal_memory::MemoryBlock;
 
     use crate::{M68k, M68kType};
@@ -330,7 +329,7 @@ mod execute_unit_tests {
     #[allow(clippy::uninit_vec)]
     fn run_execute_test<F>(cputype: M68kType, mut test_func: F)
     where
-        F: FnMut(M68kCycleExecutor<&mut MemoryBlock<u32, Instant>, Instant>),
+        F: FnMut(M68kCycleExecutor<&mut MemoryBlock<Instant>, Instant>),
     {
         // Insert basic initialization
         let len = 0x10_0000;

emulator/cpus/m68k/tests/decode_tests.rs

@@ -64,7 +64,7 @@ const DECODE_TESTS: &'static [TestCase] = &[
 ];
 
 
-fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<u32, Instant>) {
+fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<Instant>) {
     // Insert basic initialization
     let len = 0x2000;
     let mut data = Vec::with_capacity(len);

emulator/cpus/m68k/tests/execute_tests.rs

@@ -37,7 +37,7 @@ struct TestCase {
 #[allow(clippy::uninit_vec)]
 fn run_execute_test<F>(cputype: M68kType, mut test_func: F)
 where
-    F: FnMut(M68kCycleExecutor<&mut MemoryBlock<u32, Instant>, Instant>),
+    F: FnMut(M68kCycleExecutor<&mut MemoryBlock<Instant>, Instant>),
 {
     // Insert basic initialization
     let len = 0x10_0000;

emulator/cpus/m68k/tests/musashi_timing_tests.rs

@@ -12,7 +12,7 @@ const INIT_STACK: M68kAddress = 0x00002000;
 const INIT_ADDR: M68kAddress = 0x00000010;
 
 #[allow(clippy::uninit_vec)]
-fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<u32, Instant>) {
+fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<Instant>) {
     // Insert basic initialization
     let len = 0x10_0000;
     let mut data = Vec::with_capacity(len);

emulator/cpus/m68k/tests/timing_tests.rs

@@ -26,7 +26,7 @@ const TIMING_TESTS: &'static [TimingCase] = &[TimingCase {
 }];
 
 
-fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<u32, Instant>) {
+fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, MemoryBlock<Instant>) {
     // Insert basic initialization
     let len = 0x10_0000;
     let mut data = Vec::with_capacity(len);

emulator/cpus/z80/Cargo.toml

@@ -10,5 +10,11 @@ femtos = "0.1"
 emulator-hal = { path = "../../libraries/emulator-hal/emulator-hal", features = ["femtos"] }
 
 # TODO the goal is to make these optional, or remove them entirely
-moa-core = { path = "../../core" }
+moa-core = { path = "../../core", optional = true }
 moa-signals = { path = "../../libraries/signals" }
+
+[dev-dependencies]
+emulator-hal-memory = { path = "../../libraries/emulator-hal/emulator-hal-memory" }
+
+[features]
+moa = ["moa-core"]

emulator/cpus/z80/src/decode.rs

@@ -1,7 +1,7 @@
 use core::fmt::Write;
 use emulator_hal::{BusAccess, Instant as EmuInstant};
 
-use crate::state::{Z80Error, Z80Address};
+use crate::state::{Z80Error, Z80Address, Z80AddressSpace};
 use crate::instructions::{
     Direction, Condition, Register, RegisterPair, IndexRegister, IndexRegisterHalf, SpecialRegister, InterruptMode, Target,
     LoadTarget, UndocumentedCopy, Instruction,
@@ -44,7 +44,7 @@ impl Z80Decoder {
 impl Z80Decoder {
     pub fn decode_at<Bus>(bus: &mut Bus, clock: Bus::Instant, start: Z80Address) -> Result<Self, Z80Error>
     where
-        Bus: BusAccess<Z80Address>,
+        Bus: BusAccess<Z80AddressSpace>,
     {
         let mut decoder: DecodeNext<'_, Bus, Bus::Instant> = DecodeNext {
             clock,
@@ -57,7 +57,7 @@ impl Z80Decoder {
 
     pub fn dump_disassembly<Bus>(bus: &mut Bus, start: Z80Address, length: Z80Address)
     where
-        Bus: BusAccess<Z80Address>,
+        Bus: BusAccess<Z80AddressSpace>,
     {
         let mut next = start;
         while next < (start + length) {
@@ -76,27 +76,27 @@ impl Z80Decoder {
 
     pub fn dump_decoded<Bus>(&mut self, bus: &mut Bus)
     where
-        Bus: BusAccess<Z80Address>,
+        Bus: BusAccess<Z80AddressSpace>,
     {
         let ins_data = self.format_instruction_bytes(bus);
         println!("{:#06x}: {}\n\t{:?}\n", self.start, ins_data, self.instruction);
     }
 
     pub fn format_instruction_bytes<Bus>(&mut self, bus: &mut Bus) -> String
     where
-        Bus: BusAccess<Z80Address>,
+        Bus: BusAccess<Z80AddressSpace>,
     {
         let mut ins_data = String::new();
         for offset in 0..self.end.saturating_sub(self.start) {
-            write!(ins_data, "{:02x} ", bus.read_u8(Bus::Instant::START, self.start + offset).unwrap()).unwrap()
+            write!(ins_data, "{:02x} ", bus.read_u8(Bus::Instant::START, Z80AddressSpace::Memory(self.start + offset)).unwrap()).unwrap()
         }
         ins_data
     }
 }
 
 pub struct DecodeNext<'a, Bus, Instant>
 where
-    Bus: BusAccess<Z80Address, Instant = Instant>,
+    Bus: BusAccess<Z80AddressSpace, Instant = Instant>,
 {
     clock: Instant,
     bus: &'a mut Bus,
@@ -105,7 +105,7 @@ where
 
 impl<'a, Bus, Instant> DecodeNext<'a, Bus, Instant>
 where
-    Bus: BusAccess<Z80Address, Instant = Instant>,
+    Bus: BusAccess<Z80AddressSpace, Instant = Instant>,
     Instant: EmuInstant,
 {
     pub fn decode_one(&mut self) -> Result<(), Z80Error> {
@@ -579,7 +579,7 @@ where
     fn read_instruction_byte(&mut self) -> Result<u8, Z80Error> {
         let byte = self
             .bus
-            .read_u8(self.clock, self.decoder.end)
+            .read_u8(self.clock, Z80AddressSpace::Memory(self.decoder.end))
             .map_err(|err| Z80Error::BusError(format!("{:?}", err)))?;
         self.decoder.end = self.decoder.end.wrapping_add(1);
         Ok(byte)
@@ -590,7 +590,7 @@ where
         for byte in bytes.iter_mut() {
             *byte = self
                 .bus
-                .read_u8(self.clock, self.decoder.end & 0xFFFF)
+                .read_u8(self.clock, Z80AddressSpace::Memory(self.decoder.end & 0xFFFF))
                 .map_err(|err| Z80Error::BusError(format!("{:?}", err)))?;
             self.decoder.end = self.decoder.end.wrapping_add(1);
         }