Commands

Command Lists

• add_hdl_source()

add_hdl_source()

Add HDL source file VHDL, Verilog or SystemVerilog to project.

add_hdl_source(hdl_source_file
    [NAME hdl_name]
    [TYPE hdl_type]
    [SOURCE hdl_source_file]
    [TARGET hdl_target_name]
    [LIBRARY hdl_library_name]
    [SOURCES hdl_source...]
    [DEPENDS hdl_dependency...]
    [DEFINES hdl_define...]
    [INCLUDES hdl_include_dir...]
    [PACKAGE <TRUE|FALSE>]
    [SYNTHESIZABLE <TRUE|FALSE>]
    [MIF_FILES mif_file...]
    [TEXT_FILES text_file...]
    [INPUT_FILES input_file...]
    [MODELSIM_LINT <TRUE|FALSE>]
    [MODELSIM_PEDANTICERRORS <TRUE|FALSE>]
    [MODELSIM_WARNINGS_AS_ERROR <TRUE|FALSE>]
    [MODELSIM_SUPPRESS modelsim_suppresss_error_number...]
    [OUTPUT_LIBRARIES var]
    [OUTPUT_INCLUDES var]
    [OUTPUT_WORKING_DIRECTORY var]
    [QUARTUS_IP_FILES ip_file...]
    [QUARTUS_SDC_FILES sdc_file...]
    [QUARTUS_QSYS_FILES qsys_file...]
    [QUARTUS_QSYS_TCL_FILES qsys_tcl_file...]
    [COMPILE_EXCLUDE <Vivado|Quartus|ModelSim|Verilator>...]
    [COMPILE <TRUE|FALSE|Vivado|Quartus|ModelSim|Verilator>...]
    [ANALYSIS <TRUE|FALSE|Vivado|Quartus|ModelSim|Verilator>...]
)

Examples

Adding HDL source file to project:

add_hdl_source(my_hdl_module.sv)

Properties

• NAME

HDL module name. If not provided, HDL name will be taken from HDL source file name without file type extension. Good HDL practice is to keep HDL module name exactly as HDL source file name and only single declared HDL module per single file. HDL name should be unique and global for avoiding name clashing in current project and imported (re-used) in other projects.

• ANALYSIS

Enable or disable HDL source file analysis using different simulation, lint or synthesis tools. On default this property is set to FALSE. When is set to TRUE it will use all detected tools during CMake configuration for analyzing HDL source file. You can choose one or more analysis tools separate by whitespaces. Available options:

• Vivado
• Quartus
• ModelSim
• Verilator

Example:

add_hdl_source(my_hdl_module_1.sv
    ANALYSIS
        ModelSim Quartus
)

add_hdl_source(my_hdl_module_2.sv
    ANALYSIS
        TRUE
)