Verilog_codes_synthesised_using_yosys

These are verilog codes that are synthesized using open source tool yosys
Understanding what is synthesis is important. Anyone can produce the synthesized netlist once we give codes. Understanding the entire process of Logic syntheis helps us make less errors, synthesize effectively and also read results in a better manner. Logic synthesis consists of various steps - The first one begin RTL synthesis, then logic optimization, then technology mapping and then finally technology mapped optimization.
RTL synthesis is the first step of logic synthesis. In this step the verilog code is converted to netlist consisting of generic logic gates. This is further divided into parsing, elaboration and then finally optimization+translation. This step is important as it tells us how the synthesis tool converts the verilog code to syntax tree (known as parsing) and then this is converted to internal model representation. We should also be aware of what is sythesizable and what is not.
After RTL synthesis, we have logic optimization on generic netlist generated by previous step. This is of two types - 2 level (usually done using Quine's algorithm and aims to find minimal cover) and multilevel logic optimization ( Having idea about directed acyclic graph(boolean logic network) and factored form and various multilevel logic optimization techniques such as eliminate, simplify, extract and substitute help in understanding how the tool optimizes).
Then we have technology mapping where we map the netllist to a standard cell present in the library using proess design kit(PDK). The information of area, delay, power and many such information is present in the library in the form of hierarchy. We should know why the creation of libaries is done and what is the information present in libraries and what are the various modelling schemes used in libaries to model delays, power , etc (NLDM, ECS, CCS, lumped modelling of RC interconnects, distributed modelling of RC and so on). So, in this step we perform technology mapping .
In the final step we do optimization on technology mapped netlist
Having idea about hypercubes, SAT solvers, ROBDD (reduced ordered binary decision diagrams) and much more concepts related to how the tool reads verilog language, uses information from libary, generates netlist and does logic optimization. It also explains how the circuits can be automated to such a great level of abstraction using data structures which model behavior of circuits.

1. FULL ADDER (1 BIT) :

a. Full adder code -

module top(a,b, cin, sum, co) ;
input a,b, cin;
output sum, co;
assign sum=a^b^cin;
assign co=(a&b) | (a&c) | (b&c) ;
endmodule

b. Internal model representation - This is known as syntax tree. This is the first stage of RTL synthesis known as parsing.

c. Technlogy mapping -

I used a 45nm pdk and typical process to do technology mapping. I created a yosys script instead of giving individual commands. The script is -
#read design
read_verilog top.v
#elaborate design hierarchy
hierarchy -check -top top
#mapping to internal cell library
synth -top top
#mapping flip-flops to mycells.lib
#dfflibmap -liberty NangateOpenCellLibrary_typical.lib
#mapping logic to mycells.lib
abc -liberty NangateOpenCellLibrary_typical.lib
#cleanup
clean
#write synthesized design
write_verilog -noattr synth.v

I got the following netlist -

2. 4:1 demux

a. Code -

module demux(out0,out1,out2,out3,s1,s0,in);
output out0,out1,out2,out3;
reg out0,out1,out2,out3;
input s1,s0,in;
always @(in or s1 or s0)
case({s1,s0})
2'b00: begin out0=in;out1=1'bz;out2=1'bz;out3=1'bz; end
2'b01: begin out0=1'bz;out1=in;out2=1'bz;out3=1'bz; end
2'b10: begin out0=1'bz;out1=1'bz;out2=in;out3=1'bz; end
2'b11: begin out0=1'bz;out1=1'bz;out2=1'bz;out3=in; end
2'b1x,2'b0x,2'bx1,2'bx0,2'bxx,2'bzx,2'bxz : begin
out0=1'bx;out1=1'bx;out2=1'bx;out3=1'bx; end
2'b1z,2'b0z,2'bz1,2'bz0,2'bzz : begin
out0=1'bz;out1=1'bz;out2=1'bz;out3=1'bz; end
default :$display("Invalid select signal");
endcase
endmodule

b. Internal model representation -

c. Technlogy mapping -

I used a 45nm pdk and typical process to do technology mapping. I created a tcl script instead of giving individual commands. The script is -

#read modules from Verilog file
read_verilog top.v

hierarchy -check -top top

#translate processes to netlists
proc

#mapping to internal cell library
techmap

#mapping flip-flops to NangateOpenCellLibrary_typical.lib
#for eg. always block

dfflibmap -liberty NangateOpenCellLibrary_typical.lib

#mapping logic to NangateOpenCellLibrary_typical.lib
#for eg. assign block
abc -liberty NangateOpenCellLibrary_typical.lib

#remove unused cells and wires
clean
#Write the current design to a Verilog file
write_verilog -noattr synth_example.v

d. Chip area calculation -

Using the command : stat -liberty NangateOpenCellLibrary_typical.lib

3. FULL ADDER (4 BIT) using structural abstraction :

a. Internal model representation -

4. FULL ADDER (4 BIT) using dataflow :

a. Internal model representation -

b. Technlogy mapping -

c. Area -

5. Edge detector :

a. Internal model representation -

b. Technology mapping -

c. Area -

6. BCD counter :

a. Internal model representation -

b. Technology mapping -

c. Area -

7. Carry look ahead adder (4 bit) :

a. Internal model representation -

b. Technology mapping -

c. Area -

8 Overflow detector :

a. Generic logic gate -
I used different set of commands this time. Instead of generating a internal model, I generated a generic logic gate netlist using the following command - read_verilog top.v;
synth -top top;
write_verilog top_netlist.v

b. Generic gate logic optimization -
read_verilog mydesign.v;
synth;
opt;
clean;
write_verilog mydesign_optimized.v

c. Technology mapping -
I also updated the technology mapping commands to get a better view of the gates and mapping -
read_liberty -lib NangateOpenCellLibrary_typical.lib
read_verilog top.v
proc techmap
dfflibmap -liberty NangateOpenCellLibrary_typical.lib
abc -liberty NangateOpenCellLibrary_typical.lib
write_verilog -noattr top_mapped.v

br>

d. Area -

d. Logic Optimization -
Commands opt was given
Also resource sharing was made possible using the command share -aggressive

SAT word used above stands for Satisfiability solvers. SAT solvers and ROBDD are used extensively for represetation of Boolean functions. They are canonical and compact and make optimization and verification of circuits easier.

9 FSM to detect more than one 1s in the last 3 samples :

a. Internal model representation -

b. Generic logic gate -

c. Optimized Generic logic gate -

d. Technology mapped optimised netlist -

e. Area -

This is the end of repository, the learning about yosys is complete. After this point it is very easy to go look up their doc and read what individual command does and then use it. With this knowledge, it should be easy to synthesize any circuit easily.......