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Micro-optimization
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WrathfulSpatula committed Nov 13, 2024
1 parent 4522b2f commit 9758561
Showing 1 changed file with 6 additions and 6 deletions.
12 changes: 6 additions & 6 deletions src/qengine/arithmetic.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -728,7 +728,7 @@ void QEngineCPU::INCBCD(const bitCapInt& toAdd, bitLenInt inOutStart, bitLenInt
return;
}

const bitLenInt nibbleCount = length / 4;
const bitLenInt nibbleCount = length >> 2U;
if (nibbleCount * 4 != (int)length) {
throw std::invalid_argument("BCD word bit length must be a multiple of 4.");
}
Expand Down Expand Up @@ -801,7 +801,7 @@ void QEngineCPU::INCDECBCDC(const bitCapInt& toMod, bitLenInt inOutStart, bitLen
return;
}

const bitLenInt nibbleCount = length / 4;
const bitLenInt nibbleCount = length >> 2U;
if (nibbleCount * 4 != (int)length) {
throw std::invalid_argument("BCD word bit length must be a multiple of 4.");
}
Expand Down Expand Up @@ -898,7 +898,7 @@ bitCapInt QEngineCPU::IndexedLDA(bitLenInt indexStart, bitLenInt indexLength, bi
SetReg(valueStart, valueLength, ZERO_BCI);
}

const bitLenInt valueBytes = (valueLength + 7U) / 8U;
const bitLenInt valueBytes = (valueLength + 7U) >> 3U;
const bitCapIntOcl inputMask = bitRegMaskOcl(indexStart, indexLength);
const bitCapIntOcl skipPower = pow2Ocl(valueStart);

Expand Down Expand Up @@ -995,7 +995,7 @@ bitCapInt QEngineCPU::IndexedADC(bitLenInt indexStart, bitLenInt indexLength, bi
// already know the carry is zero). This bit masks let us quickly
// distinguish the different values of the input register, output register,
// carry, and other bits that aren't involved in the operation.
const bitLenInt valueBytes = (valueLength + 7U) / 8U;
const bitLenInt valueBytes = (valueLength + 7U) >> 3U;
const bitCapIntOcl lengthPower = pow2Ocl(valueLength);
const bitCapIntOcl carryMask = pow2Ocl(carryIndex);
const bitCapIntOcl inputMask = bitRegMaskOcl(indexStart, indexLength);
Expand Down Expand Up @@ -1110,7 +1110,7 @@ bitCapInt QEngineCPU::IndexedSBC(bitLenInt indexStart, bitLenInt indexLength, bi
// We're going to loop over every eigenstate in the vector, (except, we already know the carry is zero).
// This bit masks let us quickly distinguish the different values of the input register, output register, carry, and
// other bits that aren't involved in the operation.
const bitLenInt valueBytes = (valueLength + 7U) / 8U;
const bitLenInt valueBytes = (valueLength + 7U) >> 3U;
const bitCapIntOcl lengthPower = pow2Ocl(valueLength);
const bitCapIntOcl carryMask = pow2Ocl(carryIndex);
const bitCapIntOcl inputMask = bitRegMaskOcl(indexStart, indexLength);
Expand Down Expand Up @@ -1191,7 +1191,7 @@ void QEngineCPU::Hash(bitLenInt start, bitLenInt length, const unsigned char* va

CHECK_ZERO_SKIP();

const bitLenInt bytes = (length + 7U) / 8U;
const bitLenInt bytes = (length + 7U) >> 3U;
const bitCapIntOcl inputMask = bitRegMaskOcl(start, length);

Finish();
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