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Adding Documentation
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unknownK19 committed May 20, 2024
1 parent d75f99c commit 21a5c55
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Showing 3 changed files with 31 additions and 13 deletions.
1 change: 1 addition & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@ name = "logic_trioxide"
version = "0.1.0"
edition = "2021"
authors = ["Anurag"]
description = "A simple Logic Gate simulating Library"

[dependencies]

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14 changes: 8 additions & 6 deletions examples/example01.rs
Original file line number Diff line number Diff line change
@@ -1,21 +1,23 @@
use logic_o3::logic::{Circuit, LogicCircuit};

fn main() {
// Add Two Logic Gate
let and1 = LogicCircuit::new(logic_o3::logic::LogicGate::AND);
let not1 = LogicCircuit::new(logic_o3::logic::LogicGate::NOT);

// Create New Circuit
let mut nand = Circuit::new();

// Insert Two Logic Gate
nand.add_logic_gate(and1);
nand.add_logic_gate(not1);

// Connect wire between Two Gate
nand.connection_scheme((0, 1, 0));

// Add Input Signal on Circuit
nand.add_input_connection((true, vec![(0, 0)]));
nand.add_input_connection((false, vec![(0, 1)]));

// Add Output Signal to know Output of this Circuit
nand.add_output_connection(1);

// Update Cicuit in According to Input
nand.update();
// TADA !!
println!("{:?}", nand.know_output());
}
29 changes: 22 additions & 7 deletions src/logic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ pub struct Circuit {
}

impl Circuit {
/// Create Circuit
pub fn new() -> Self {
Self {
component: vec![],
Expand All @@ -18,9 +19,11 @@ impl Circuit {
output: vec![],
}
}
/// Add component AKA LogicCircuit
pub fn add_logic_gate(&mut self, new_comp: LogicCircuit) {
self.component.push(new_comp)
}
/// Connect Between Component
pub fn connection_scheme(&mut self, connection: (usize, usize, usize)) {
if self.component.len() < connection.0 {
dbg!(println!(
Expand All @@ -29,6 +32,7 @@ impl Circuit {
}
self.connection_path.push(connection)
}
/// Add Input on Circuit
pub fn add_input(&mut self, no_of_input: usize) {
match no_of_input {
0 => dbg!(println!("WARNING: Number of Input Cannot be Zero")),
Expand All @@ -39,14 +43,17 @@ impl Circuit {
}
}
}
/// Add Input with connection
pub fn add_input_connection(&mut self, connection: (bool, Vec<(usize, usize)>)) {
self.input.push(Rc::new(RefCell::new(connection)))
}
/// Change Input Signal
pub fn change_input_signal(&mut self, input_index: usize, change_to: bool) {
match *(*self.input[input_index]).borrow_mut() {
(ref mut signal, _) => *signal = change_to,
}
}
/// Add Input config to attach component AKA wiring between LogicCircuit and Input Signal
pub fn change_input_config(
&mut self,
connection: (bool, Vec<(usize, usize)>),
Expand All @@ -60,21 +67,26 @@ impl Circuit {
*(*self.input[input_index]).borrow_mut() = connection
}
}
/// Add Output Signal to know Output.
pub fn add_output_connection(&mut self, comp_id: usize) {
self.output
.push(Rc::new(RefCell::new((vec![comp_id], false))))
}
pub fn add_comp_onoutput(&mut self, comp_id: usize, at_index: usize) {
match *(*self.output[at_index]).borrow_mut() {
/// Adding more comp on specific Output
pub fn add_comp_onoutput(&mut self, comp_id: usize, output_index: usize) {
match *(*self.output[output_index]).borrow_mut() {
(ref mut x, _) => x.push(comp_id),
}
}
/// Know Number of output
pub fn know_no_output(&self) -> usize {
self.output.len()
}
/// Know Output on Specific component
pub fn know_output_comp(&self, comp_id: usize) -> bool {
*(*self.component[comp_id].output).borrow_mut()
}
/// Know Output of Circuit
pub fn know_output(&mut self) -> Vec<bool> {
let mut out = vec![];
for out_each in self.output.clone() {
Expand All @@ -84,6 +96,7 @@ impl Circuit {
}
out
}
/// Refresh The Cicuit to update Output
pub fn update(&mut self) {
let mut count = 0;
{
Expand Down Expand Up @@ -134,22 +147,21 @@ impl Circuit {
}
}
}
//TODO
//TODO: Add removing specific comp also destroy connected connection
}

pub enum LogicGate {
AND, // AND Gate
NOT,
OR,
/*More TODO*/
NOT, // NOT Gate
OR, // OR Gate
}

pub struct LogicCircuit {
input: Vec<Rc<RefCell<bool>>>, // Input pin indexing like [true, false, false, false]
gate_type: LogicGate, // Which Logic Gate
output: Rc<RefCell<bool>>, // Single output pin
}

/// To Know LogicCircuit Current supply.
impl ToString for LogicCircuit {
fn to_string(&self) -> String {
use LogicGate::{AND, NOT, OR};
Expand Down Expand Up @@ -193,6 +205,7 @@ impl ToString for LogicCircuit {
}

impl LogicCircuit {
/// Create LogicCircuit
pub fn new(logic_type: LogicGate) -> Self {
match logic_type {
LogicGate::NOT => LogicCircuit {
Expand All @@ -211,6 +224,7 @@ impl LogicCircuit {
}
}
}
/// Add LogicCircuit with number of pins
pub fn new_with_pins(logic_type: LogicGate, number: usize) -> Self {
match number {
0 | 1 => panic!("Zero or One It sould not Exist"),
Expand All @@ -231,6 +245,7 @@ impl LogicCircuit {
},
}
}
/// To update the LogicCircuit
pub fn update(&mut self) {
use LogicGate::{AND, NOT, OR};
let input = |index: usize| *(*self.input[index]).borrow_mut();
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